feat: implement virtual clock timing architecture (Phases 5-8)
Introduces a VirtualClock-based timing system replacing wall-clock Instant-based timing for hardware-accurate simulation. New modules: - virtual_clock.rs: Shared virtual time source with condvar sync - real_time_governor.rs: Thread that advances virtual time - component_timing.rs: Per-component timing constraints Key changes: - Component trait: added update_at_time(), timing(), set_virtual_clock_optional() - All Intel 400x components migrated to virtual-time-aware operation - ConfigurableSystem: start() returns Result, spawns governor thread - GUI: timing controls (speed slider, mode selector, step button) - Console: speed/mode/step/time commands - Backward compatible: legacy fallback for components without VirtualClock Reviewed-by: code review found 2 warnings (clock resume() dead code, reset() safety docs) — both fixed.
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plans/timing_architecture.md
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# Timing-Accurate Simulation Architecture
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## Problem Statement
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The current emulator spawns each component in its own OS thread with independent `thread::sleep()` calls. This means:
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1. **No timing accuracy** — `nanosleep` has ~100µs granularity but components need nanosecond-level timing
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2. **No synchronization** — Components update independently with no guaranteed ordering
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3. **No speed control** — No way to slow down, speed up, or single-step
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4. **No hardware timing enforcement** — Timing constants exist but aren't checked against simulation time
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## How Other Emulators/Simulators Handle Timing
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### UAE (Ultimate Amiga Emulator)
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UAE uses a **line-based timing model**:
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- The Amiga's custom chips are synchronized to the video beam position (horizontal line)
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- Each emulated line takes a fixed number of CPU cycles (e.g., 228 cycles for PAL)
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- The CPU runs for one line's worth of cycles, then the custom chips update
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- A **host synchronization point** occurs once per frame (50/60 Hz) — UAE sleeps to match real-time at the frame boundary, not per-cycle
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- Sound output drives real-time sync: the audio buffer must be filled at the correct rate
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- Key insight: **UAE batches many cycles of work, then syncs to wall-clock at coarse granularity (frame rate)**
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### VICE (Versatile Commodore Emulator)
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VICE uses a **cycle-accurate but batched** model:
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- The CPU and CIA/VIC chips each track their own cycle count
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- The main loop runs the CPU for one cycle, then lets the VIC/CIA advance one cycle
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- **No per-cycle sleeping** — VICE runs cycles as fast as possible
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- Real-time sync happens at the **frame boundary** (50/60 Hz = every ~20ms)
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- VICE uses the host's audio subsystem or `usleep()` at frame boundaries to maintain real-time
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- The SID (sound chip) and VIC (video) generate their output in batches, then the host presents it at the right time
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- Key insight: **Cycle-accurate internally, wall-clock synced at frame boundaries**
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### Verilog/VHDL Simulators (Icarus Verilog, ModelSim, Verilator)
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- **Event-driven scheduling** at virtual time points
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- Components register callbacks: "wake me at virtual time T"
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- No wall-clock sleeping at all — pure computation
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- The simulator maintains an **event queue** sorted by virtual time
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- Key insight: **Virtual time is just a number in a priority queue**
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### QEMU
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- Uses **instruction counting** for timing
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- Each emulated instruction advances a virtual clock counter
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- For real-time workloads (audio, video), QEMU sleeps at coarse boundaries
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- Key insight: **Count instructions, sync at coarse intervals**
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### SPICE (Analog Simulator)
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- **Adaptive timestep** integration
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- Time advances in variable-size steps based on signal activity
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- Smaller steps when signals change rapidly, larger steps when stable
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- Key insight: **Variable granularity based on activity**
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### Common Pattern
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All these emulators share the same core pattern:
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```mermaid
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graph LR
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A[Run N cycles of virtual time] --> B[Batch: process all events for those cycles]
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B --> C[Sync: sleep to match wall-clock if needed]
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C --> A
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```
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The **sync point granularity** varies:
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| Emulator | Sync granularity | Virtual time per sync |
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|----------|-----------------|----------------------|
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| UAE | Per video frame | ~20ms |
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| VICE | Per video frame | ~20ms |
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| QEMU | Per instruction batch | ~1-10ms |
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| Verilog | Never (pure computation) | N/A |
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| SPICE | Never (pure computation) | N/A |
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**The key insight for our emulator:** We should use **virtual time internally** (like all of them) and **sync to wall-clock at coarse boundaries** (like UAE/VICE), not try to `nanosleep` per cycle.
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---
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## Proposed Architecture: Virtual-Time-Synchronized Per-Component Threads
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### Core Idea
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Keep each component in its own thread (the project's signature feature), but replace `thread::sleep()`-based timing with a **shared virtual clock** that all components synchronize against. Components sleep until the virtual clock reaches their next scheduled update time.
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### Architecture Diagram
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```mermaid
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graph TB
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subgraph "Global Synchronization"
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VC[VirtualClock - shared Arc atomic u64 nanoseconds]
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RTG[RealTimeGovernor - advances virtual clock]
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SC[SpeedControl - multiplier + mode]
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end
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subgraph "Component Threads - each runs independently"
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CT1[Clock Thread]
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CT2[CPU Thread]
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CT3[ROM Thread]
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CT4[RAM Thread]
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CT5[ShiftReg Thread]
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end
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subgraph "Per-Component Timing"
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T1[ComponentTiming - access_time, setup_time, etc.]
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T2[TimingChecker - validates constraints against virtual time]
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end
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RTG --> VC
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SC --> RTG
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VC --> CT1
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VC --> CT2
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VC --> CT3
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VC --> CT4
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VC --> CT5
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T1 --> CT2
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T1 --> CT3
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T2 --> CT3
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```
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### How It Works — Virtual Time Synchronization
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```mermaid
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sequenceDiagram
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participant Gov as Governor Thread
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participant VC as VirtualClock
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participant CLK as Clock Thread
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participant CPU as CPU Thread
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participant ROM as ROM Thread
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Note over Gov: Governor advances virtual clock in steps
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Gov->>VC: advance to 333ns
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VC->>VC: notify_all - wake sleeping components
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CLK->>VC: read virtual_time = 333ns
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CLK->>CLK: 333ns >= 666ns? No - sleep until 666ns
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CPU->>VC: read virtual_time = 333ns
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CPU->>CPU: Check for clock edges - no change - wait
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Note over Gov: Governor advances
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Gov->>VC: advance to 666ns
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VC->>VC: notify_all
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CLK->>VC: read virtual_time = 666ns
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CLK->>CLK: 666ns >= 666ns? Yes! Toggle PHI1 LOW, PHI2 HIGH
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CLK->>CLK: Schedule next transition at 1333ns
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CLK->>VC: wait_until 1333ns
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CPU->>VC: read virtual_time = 666ns
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CPU->>CPU: Detect PHI2 rising - process data phase
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ROM->>VC: read virtual_time = 666ns
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ROM->>ROM: See address on bus. Record latch_time = 666ns
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ROM->>ROM: Need 500ns access time. Data ready at 1166ns
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ROM->>VC: wait_until 1166ns
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Note over Gov: Governor advances
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Gov->>VC: advance to 1166ns
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ROM->>VC: read virtual_time = 1166ns
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ROM->>ROM: 1166 - 666 = 500ns >= 500ns access time. Drive data!
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```
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---
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## Key Components
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### 1. VirtualClock — Shared Virtual Time Source
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```rust
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pub struct VirtualClock {
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/// Current virtual time in nanoseconds
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time_ns: AtomicU64,
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/// Target time for next step (components wait for this)
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target_ns: AtomicU64,
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/// Condvar for notifying components when time advances
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time_advanced: Condvar,
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/// Mutex for condvar
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state_mutex: Mutex<()>,
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/// Speed multiplier: 1.0 = real-time, 0.1 = 10x slower
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speed_multiplier: AtomicU64, // Stored as fixed-point
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/// Simulation mode
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mode: AtomicU8, // 0=RealTime, 1=MaxSpeed, 2=SingleStep
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/// Single-step trigger
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step_pending: AtomicBool,
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}
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impl VirtualClock {
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/// Get current virtual time
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pub fn now(&self) -> Duration {
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Duration::from_nanos(self.time_ns.load(Ordering::SeqCst))
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}
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/// Block until virtual time reaches at least target
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/// Returns the actual virtual time when woken
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pub fn wait_until(&self, target: Duration) -> Duration {
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let target_ns = target.as_nanos() as u64;
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self.target_ns.store(target_ns, Ordering::SeqCst);
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loop {
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let current = self.time_ns.load(Ordering::SeqCst);
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if current >= target_ns {
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return Duration::from_nanos(current);
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}
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// Wait for governor to advance time
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let guard = self.state_mutex.lock();
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self.time_advanced.wait(guard);
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}
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}
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/// Non-blocking check: has virtual time reached target?
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pub fn has_reached(&self, target: Duration) -> bool {
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self.time_ns.load(Ordering::SeqCst) >= target.as_nanos() as u64
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}
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}
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```
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### 2. RealTimeGovernor — Advances Virtual Clock
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Runs in its own thread. Advances the shared virtual clock based on speed multiplier:
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```rust
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pub struct RealTimeGovernor {
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clock: Arc<VirtualClock>,
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tick_size_ns: u64, // Virtual nanoseconds per tick (e.g., 333)
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speed_multiplier: f64, // 1.0 = real-time
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}
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impl RealTimeGovernor {
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fn run(&mut self) {
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let mut last_wall_time = Instant::now();
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loop {
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match self.clock.mode() {
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SimulationMode::RealTime => {
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// Calculate how long to sleep to match speed_multiplier
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let virtual_advance = Duration::from_nanos(self.tick_size_ns);
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let target_wall = virtual_advance.div_f64(self.speed_multiplier);
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let elapsed = last_wall_time.elapsed();
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if elapsed < target_wall {
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thread::sleep(target_wall - elapsed);
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}
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// Advance virtual time
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self.clock.advance_by(self.tick_size_ns);
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last_wall_time = Instant::now();
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}
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SimulationMode::MaxSpeed => {
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// Advance as fast as possible
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self.clock.advance_by(self.tick_size_ns);
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// Yield occasionally to prevent starving other threads
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if self.clock.now().as_nanos() % 1000 == 0 {
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thread::yield_now();
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}
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}
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SimulationMode::SingleStep => {
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// Wait for user to trigger a step
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if self.clock.consume_step_trigger() {
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self.clock.advance_by(self.tick_size_ns);
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} else {
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thread::sleep(Duration::from_millis(1));
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}
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}
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}
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}
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}
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}
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```
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### 3. Component Thread Pattern
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Each component thread follows this pattern:
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```rust
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// In ConfigurableSystem::start() — for each component:
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let clock_clone = Arc::clone(&virtual_clock);
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let comp_clone = Arc::clone(&component);
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thread::spawn(move || {
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let mut next_update_time = Duration::ZERO;
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let timing = ComponentTiming::for_component(&*comp_clone.lock());
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loop {
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// Wait for virtual time to reach our next scheduled update
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let current_vtime = clock_clone.wait_until(next_update_time);
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if !clock_clone.is_running() {
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break;
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}
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// Lock component and update
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if let Some(mut comp) = comp_clone.try_lock() {
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comp.update_at_time(current_vtime);
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}
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// Schedule next update based on component's timing needs
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next_update_time = current_vtime + timing.minimum_update_interval();
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}
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});
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```
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### 4. Per-Component Timing with Virtual Time
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Components use virtual time instead of `Instant::now()`:
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```rust
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// In Intel4001 (ROM):
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impl Component for Intel4001 {
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fn update_at_time(&mut self, virtual_time: Duration) {
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let (phi1, phi2) = self.read_clock_pins();
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let phi1_rising = phi1 == PinValue::High && self.prev_phi1 == PinValue::Low;
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if phi1_rising {
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// Record when address was latched (in virtual time!)
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self.address_latch_time = Some(virtual_time);
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self.handle_phi1_rising();
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}
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if phi2_rising {
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// Check if access time has elapsed IN VIRTUAL TIME
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if let Some(latch_time) = self.address_latch_time {
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let elapsed_virtual = virtual_time.saturating_sub(latch_time);
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if elapsed_virtual >= self.timing.access_time {
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// Data is valid — drive it
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self.handle_phi2_rising();
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} else {
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// Access time NOT yet elapsed — data not ready!
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// This happens when the clock is overclocked
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self.handle_data_not_ready();
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}
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}
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}
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self.prev_phi1 = phi1;
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self.prev_phi2 = phi2;
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}
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}
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```
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### 5. Clock Component with Virtual Time
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```rust
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// In TwoPhaseClock:
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impl Component for TwoPhaseClock {
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fn update_at_time(&mut self, virtual_time: Duration) {
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// Check if it's time to transition (using virtual time)
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let elapsed = virtual_time.saturating_sub(self.last_transition_vtime);
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match self.current_phase {
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Phase::Phi1High => {
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if elapsed >= self.phase_time {
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self.phi1_state = PinValue::Low;
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self.phi2_state = PinValue::High;
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self.last_transition_vtime = virtual_time;
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self.update_outputs();
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}
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}
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Phase::Phi2High => {
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if elapsed >= self.phase_time {
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self.phi2_state = PinValue::Low;
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self.phi1_state = PinValue::High;
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self.last_transition_vtime = virtual_time;
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self.update_outputs();
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}
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}
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}
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}
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}
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```
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---
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## Thread Architecture
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```mermaid
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graph LR
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subgraph "Governor Thread"
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G[RealTimeGovernor]
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G -->|advance_by tick_size| VC[VirtualClock]
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end
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subgraph "Component Thread 1"
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C1[TwoPhaseClock]
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C1 -->|wait_until next_transition| VC
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end
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subgraph "Component Thread 2"
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C2[Intel4004]
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C2 -->|wait_until next_cycle| VC
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end
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subgraph "Component Thread 3"
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C3[Intel4001]
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C3 -->|wait_until access_time_elapsed| VC
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end
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subgraph "Component Thread N"
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CN[...]
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CN -->|wait_until scheduled_time| VC
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end
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VC -->|notify_all on advance| C1
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VC -->|notify_all on advance| C2
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VC -->|notify_all on advance| C3
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VC -->|notify_all on advance| CN
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```
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Each component thread:
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1. Calls `virtual_clock.wait_until(target_time)` — blocks until the governor advances virtual time past the target
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2. Wakes up, reads pins, processes its logic
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3. Schedules its next wake-up time based on its timing constraints
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4. Goes back to sleep
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The governor thread:
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1. Advances virtual time by `tick_size` (e.g., 333ns)
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2. Notifies all waiting component threads
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3. Sleeps to match wall-clock time × speed_multiplier (if in RealTime mode)
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---
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## Component Timing Model
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```rust
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pub struct ComponentTiming {
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pub access_time: Duration, // Time from address valid to data ready
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pub propagation_delay: Duration, // Output delay after input change
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pub setup_time: Duration, // Input stability before clock edge
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pub hold_time: Duration, // Input stability after clock edge
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pub max_clock_frequency: f64, // Maximum supported clock frequency
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pub min_update_interval: Duration, // How often update_at_time should be called
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}
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// Per-component defaults from datasheets:
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impl Intel4001 { // ROM - 500ns access
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fn timing() -> ComponentTiming {
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ComponentTiming {
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access_time: Duration::from_nanos(500),
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propagation_delay: Duration::from_nanos(200),
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setup_time: Duration::from_nanos(100),
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hold_time: Duration::from_nanos(50),
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max_clock_frequency: 750_000.0,
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min_update_interval: Duration::from_nanos(100), // Check every 100ns
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}
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}
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}
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impl Intel4002 { // RAM - 500ns access
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fn timing() -> ComponentTiming {
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ComponentTiming {
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access_time: Duration::from_nanos(500),
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propagation_delay: Duration::from_nanos(200),
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setup_time: Duration::from_nanos(100),
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hold_time: Duration::from_nanos(50),
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max_clock_frequency: 750_000.0,
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min_update_interval: Duration::from_nanos(100),
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}
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}
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}
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impl Intel4003 { // Shift Register - faster 200ns
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fn timing() -> ComponentTiming {
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ComponentTiming {
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access_time: Duration::from_nanos(200),
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propagation_delay: Duration::from_nanos(100),
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setup_time: Duration::from_nanos(50),
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hold_time: Duration::from_nanos(30),
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max_clock_frequency: 1_000_000.0,
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min_update_interval: Duration::from_nanos(50),
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}
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}
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}
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```
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---
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||||
|
||||
## Speed Control
|
||||
|
||||
| Mode | Multiplier | Governor Behavior | Use Case |
|
||||
|------|-----------|-------------------|----------|
|
||||
| RealTime | 0.001× | Sleep 333µs per 333ns tick | Observe individual clock edges |
|
||||
| RealTime | 0.01× | Sleep 33.3µs per 333ns tick | Slow-motion debugging |
|
||||
| RealTime | 0.1× | Sleep 3.33µs per 333ns tick | Slower than real-time |
|
||||
| RealTime | 1.0× | Sleep 333ns per tick (≈ max speed) | Attempt real-time |
|
||||
| MaxSpeed | ∞ | No sleep, yield occasionally | Fastest possible simulation |
|
||||
| SingleStep | — | Advance one tick per trigger | Debug one phase at a time |
|
||||
|
||||
**At 1.0× and above**, the OS cannot keep up (333ns is below scheduling granularity). The governor will run as fast as it can and report the **actual achieved speed** (e.g., "Target: 1.0×, Achieved: 0.47×").
|
||||
|
||||
---
|
||||
|
||||
## Overclocking Behavior
|
||||
|
||||
When the clock frequency exceeds a component's `max_clock_frequency`:
|
||||
|
||||
```mermaid
|
||||
graph TD
|
||||
OC[Clock set to 2 MHz - 500ns cycle]
|
||||
ROM1[ROM access_time = 500ns]
|
||||
RAM1[RAM access_time = 500ns]
|
||||
SR1[ShiftReg access_time = 200ns]
|
||||
|
||||
OC -->|Phase = 250ns| ROM1
|
||||
OC -->|Phase = 250ns| RAM1
|
||||
OC -->|Phase = 250ns| SR1
|
||||
|
||||
ROM1 -->|250ns < 500ns| FAIL1[ROM data NOT ready - CPU reads garbage]
|
||||
RAM1 -->|250ns < 500ns| FAIL2[RAM data NOT ready - CPU reads garbage]
|
||||
SR1 -->|250ns >= 200ns| OK[ShiftReg responds correctly - its faster]
|
||||
```
|
||||
|
||||
This is **exactly what happens in real hardware** — the shift register (200ns access) keeps working while ROM/RAM (500ns access) fails.
|
||||
|
||||
---
|
||||
|
||||
## Migration Strategy
|
||||
|
||||
### Phase 1: Create VirtualClock (new file, non-breaking)
|
||||
|
||||
- New file: `src/virtual_clock.rs`
|
||||
- Contains `VirtualClock` struct with atomic virtual time, condvar, and speed control
|
||||
- No changes to existing code
|
||||
|
||||
### Phase 2: Create RealTimeGovernor (new file, non-breaking)
|
||||
|
||||
- New file: `src/real_time_governor.rs`
|
||||
- Governor thread that advances `VirtualClock` based on speed multiplier
|
||||
- No changes to existing code
|
||||
|
||||
### Phase 3: Create ComponentTiming (new file, non-breaking)
|
||||
|
||||
- New file: `src/component_timing.rs`
|
||||
- `ComponentTiming` struct and per-component defaults
|
||||
- No changes to existing code
|
||||
|
||||
### Phase 4: Extend Component trait with virtual time support
|
||||
|
||||
- Add `update_at_time(&mut self, virtual_time: Duration)` with default that calls `update()`
|
||||
- Add `timing(&self) -> ComponentTiming` with default that returns zero-delay timing
|
||||
- Backward-compatible — existing `update()` still works
|
||||
|
||||
### Phase 5: Migrate clock components to virtual time
|
||||
|
||||
- `GenericClock` and `TwoPhaseClock`: Replace `Instant::now()` with virtual time parameter
|
||||
- Clock transitions based on virtual time comparisons
|
||||
- Clocks call `virtual_clock.wait_until(next_transition)`
|
||||
|
||||
### Phase 6: Add timing enforcement to memory/CPU components
|
||||
|
||||
- Intel4001, Intel4002, Intel4003: Check access times against virtual time
|
||||
- Intel4004: Check setup/hold times
|
||||
- Record timing violations for reporting
|
||||
|
||||
### Phase 7: Update ConfigurableSystem to use VirtualClock
|
||||
|
||||
- Create `Arc<VirtualClock>` shared by all components
|
||||
- Governor thread manages virtual time advancement
|
||||
- Component threads use `virtual_clock.wait_until()` instead of `thread::sleep()`
|
||||
- Keep the per-component thread model — just change how they wait
|
||||
|
||||
### Phase 8: Add speed/step controls to GUI and console
|
||||
|
||||
- Speed slider (logarithmic: 0.001× to MaxSpeed)
|
||||
- Step buttons: Step Phase, Step Cycle, Step Instruction
|
||||
- Display: actual speed, virtual time, timing violations
|
||||
|
||||
### Phase 9: Update tests
|
||||
|
||||
- Tests use MaxSpeed mode for fast deterministic execution
|
||||
- Tests use SingleStep mode for precise state verification
|
||||
- Add overclocking tests: verify ROM fails at 2 MHz but shift register still works
|
||||
|
||||
---
|
||||
|
||||
## Key Differences from Single-Scheduler Approach
|
||||
|
||||
| Aspect | Single Scheduler | Per-Component Threads + VirtualClock |
|
||||
|--------|-----------------|--------------------------------------|
|
||||
| Threading model | 1 scheduler thread | N component threads + 1 governor thread |
|
||||
| Component autonomy | Components are passive — called by scheduler | Components are active — they wait for their own timing |
|
||||
| Realism | Less realistic — all components update in strict order | More realistic — components race independently, just like real hardware |
|
||||
| Timing enforcement | Centralized in scheduler | Distributed — each component enforces its own timing |
|
||||
| Race conditions | None — deterministic order | Possible — but that's **realistic**! Real hardware has races too |
|
||||
| Speed control | Scheduler controls tick rate | Governor controls virtual clock rate |
|
||||
| Complexity | Simpler | More complex but more faithful to hardware |
|
||||
|
||||
---
|
||||
|
||||
## Benefits
|
||||
|
||||
1. **Per-component threads preserved** — The project's signature feature remains
|
||||
2. **Hardware-accurate timing** — Each component enforces its real timing constraints
|
||||
3. **Overclocking realism** — Components fail when clocked too fast, just like real hardware
|
||||
4. **Virtual time** — No dependency on OS scheduling granularity
|
||||
5. **Speed control** — Logarithmic multiplier from 0.001× to MaxSpeed
|
||||
6. **Single-step** — Step by phase, cycle, or instruction
|
||||
7. **Realistic races** — Components compete for the bus independently, modeling real hardware behavior
|
||||
8. **Backward compatible** — Phases 1-3 are additive; existing code continues to work during migration
|
||||
Loading…
Add table
Add a link
Reference in a new issue