feat: implement virtual clock timing architecture (Phases 5-8)

Introduces a VirtualClock-based timing system replacing wall-clock
Instant-based timing for hardware-accurate simulation.

New modules:
- virtual_clock.rs: Shared virtual time source with condvar sync
- real_time_governor.rs: Thread that advances virtual time
- component_timing.rs: Per-component timing constraints

Key changes:
- Component trait: added update_at_time(), timing(), set_virtual_clock_optional()
- All Intel 400x components migrated to virtual-time-aware operation
- ConfigurableSystem: start() returns Result, spawns governor thread
- GUI: timing controls (speed slider, mode selector, step button)
- Console: speed/mode/step/time commands
- Backward compatible: legacy fallback for components without VirtualClock

Reviewed-by: code review found 2 warnings (clock resume() dead code,
reset() safety docs) — both fixed.

tests/integration_tests.rs

@@ -81,8 +81,8 @@ mod intel_4001_integration_tests {
         // Test access time configuration
         assert_eq!(rom.get_access_time(), 1);
 
-        // Test address latch time handling
-        let test_time = std::time::Instant::now();
+        // Test address latch time handling (virtual time: Duration-based)
+        let test_time = std::time::Duration::from_nanos(500);
         rom.set_address_latch_time(Some(test_time));
         assert_eq!(rom.get_address_latch_time(), Some(test_time));
     }