Fixed test failures
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c8552a1488
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0e0713c3a0
4 changed files with 83 additions and 10 deletions
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@ -742,7 +742,9 @@ impl Component for Intel4001 {
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/// Main update cycle - handles clock edge detection and operation dispatch
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/// Hardware: Responds to Φ1 and Φ2 clock edges from CPU
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fn update(&mut self) {
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println!("DEBUG: update() method called for {}", self.base.name());
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if !self.is_running() {
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println!("DEBUG: Component not running, returning");
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return;
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}
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// Handle both rising and falling edges for proper two-phase operation
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@ -1028,12 +1030,22 @@ mod tests {
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// Initially should be in idle state
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assert_eq!(rom.memory_state, MemoryState::Idle);
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// Start the component so it can process updates
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rom.base.set_running(true);
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assert!(rom.is_running());
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// Get pin references
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let sync_pin = rom.get_pin("SYNC").unwrap();
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let cm_pin = rom.get_pin("CM").unwrap();
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let ci_pin = rom.get_pin("CI").unwrap();
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let phi1_pin = rom.get_pin("PHI1").unwrap();
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// Initialize PHI1 to Low first
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{
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let mut phi1_guard = phi1_pin.lock().unwrap();
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phi1_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
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}
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// Set up memory read operation: SYNC=1, CM=1, CI=0 (memory access)
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{
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let mut sync_guard = sync_pin.lock().unwrap();
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@ -1044,15 +1056,44 @@ mod tests {
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ci_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Memory access
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}
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// Set Φ1 high
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// Set Φ1 high (creating rising edge)
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{
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let mut phi1_guard = phi1_pin.lock().unwrap();
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phi1_guard.set_driver(Some("TEST".to_string()), PinValue::High);
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}
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// Debug: Check pin states before update
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println!("DEBUG: Before update - SYNC: {:?}, CM: {:?}, CI: {:?}, PHI1: {:?}",
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sync_pin.lock().unwrap().read(),
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cm_pin.lock().unwrap().read(),
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ci_pin.lock().unwrap().read(),
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phi1_pin.lock().unwrap().read());
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// Debug: Check conditions that would trigger memory operation
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let sync = rom.read_sync_pin();
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let chip_select = rom.read_cm_rom_pin();
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let io_select = rom.read_ci_pin();
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println!("DEBUG: Conditions - sync: {}, chip_select: {}, io_select: {}, combined: {}",
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sync, chip_select, io_select, sync && chip_select && !io_select);
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// Debug: Check edge detection
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println!("DEBUG: Before update - prev_phi1: {:?}", rom.prev_phi1);
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// Debug: Check what read_clock_pins returns
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let (read_phi1, _) = rom.read_clock_pins();
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println!("DEBUG: read_clock_pins() returns PHI1: {:?}", read_phi1);
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// Debug: Check edge detection logic manually
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let phi1_rising = read_phi1 == PinValue::High && rom.prev_phi1 == PinValue::Low;
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println!("DEBUG: Manual edge detection - PHI1: {:?}, prev_phi1: {:?}, rising: {}",
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read_phi1, rom.prev_phi1, phi1_rising);
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// Update to process Φ1 rising edge
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rom.update();
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// Debug: Check edge detection results
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println!("DEBUG: After update - prev_phi1: {:?}", rom.prev_phi1);
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// Should have started memory operation and transitioned to AddressPhase
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assert_eq!(rom.memory_state, MemoryState::AddressPhase);
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println!("Memory state after Φ1 rising: {:?}", rom.memory_state);
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@ -476,8 +476,8 @@ impl Intel4002 {
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// Check for RAM operation start on Φ1 rising edge with SYNC high
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let (sync, _cm, p0, _) = self.read_control_pins();
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if sync && p0 {
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// Start RAM address phase on Φ1 rising edge
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if sync && p0 && self.ram_state == RamState::Idle {
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// Start RAM address phase on Φ1 rising edge (only when idle)
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self.start_ram_address_phase();
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}
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@ -1121,6 +1121,10 @@ mod tests {
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fn test_address_latching() {
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let mut ram = Intel4002::new_with_access_time("RAM_4002".to_string(), 1);
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// Start the component so it can process updates
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ram.base.set_running(true);
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assert!(ram.is_running());
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// Get pin references
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let sync_pin = ram.get_pin("SYNC").unwrap();
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let p0_pin = ram.get_pin("P0").unwrap();
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@ -1156,40 +1160,67 @@ mod tests {
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d3_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
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}
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// Debug: Check pin states before first update
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println!("DEBUG: Before first update - SYNC: {:?}, P0: {:?}, PHI1: {:?}",
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sync_pin.lock().unwrap().read(),
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p0_pin.lock().unwrap().read(),
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phi1_pin.lock().unwrap().read());
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// Debug: Check conditions that would trigger RAM operation
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let (sync, _cm, p0, _) = ram.read_control_pins();
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println!("DEBUG: Control pins - sync: {}, p0: {}, combined: {}", sync, p0, sync && p0);
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// Debug: Check initial clock state
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println!("DEBUG: Before first update - prev_phi1: {:?}", ram.prev_phi1);
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// High nibble
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phi1_pin
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.lock()
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.unwrap()
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.set_driver(Some("TEST".into()), PinValue::High);
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ram.update(); // rising edge -> latch high nibble
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// Debug: Check clock state after first update
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println!("DEBUG: After first update - prev_phi1: {:?}", ram.prev_phi1);
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phi1_pin
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.lock()
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.unwrap()
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.set_driver(Some("TEST".into()), PinValue::Low);
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ram.update(); // falling edge
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// Should have transitioned to AddressPhase
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// Should have transitioned to AddressPhase and latched high nibble
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assert_eq!(ram.ram_state, RamState::AddressPhase);
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assert_eq!(ram.address_high_nibble, Some(0x0));
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// Note: full_address_ready should be false until both nibbles are assembled
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// Set address low nibble (0x0) on data bus
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// Set address low nibble (0x1) on data bus - different from high nibble
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{
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let mut d0_guard = d0_pin.lock().unwrap();
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let mut d1_guard = d1_pin.lock().unwrap();
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let mut d2_guard = d2_pin.lock().unwrap();
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let mut d3_guard = d3_pin.lock().unwrap();
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d0_guard.set_driver(Some("TEST".into()), PinValue::Low);
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d0_guard.set_driver(Some("TEST".into()), PinValue::High); // Bit 0 = 1
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d1_guard.set_driver(Some("TEST".into()), PinValue::Low);
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d2_guard.set_driver(Some("TEST".into()), PinValue::Low);
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d3_guard.set_driver(Some("TEST".into()), PinValue::Low);
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}
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// Debug: Check state before low nibble
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println!("DEBUG: Before low nibble - High: {:?}, Low: {:?}, Ready: {}",
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ram.address_high_nibble, ram.address_low_nibble, ram.full_address_ready);
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// Low nibble
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phi1_pin
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.lock()
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.unwrap()
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.set_driver(Some("TEST".into()), PinValue::High);
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ram.update(); // rising edge -> latch low nibble
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// Debug: Check state after low nibble
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println!("DEBUG: After low nibble - High: {:?}, Low: {:?}, Ready: {}",
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ram.address_high_nibble, ram.address_low_nibble, ram.full_address_ready);
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phi1_pin
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.lock()
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.unwrap()
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@ -1197,8 +1228,8 @@ mod tests {
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ram.update(); // falling edge
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// Should have assembled full address and transitioned to WaitLatency
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assert_eq!(ram.last_address, 0x00);
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assert_eq!(ram.full_address_ready, true);
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assert_eq!(ram.last_address, 0x01); // High nibble 0x0, low nibble 0x1 = 0x01
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assert_eq!(ram.full_address_ready, true); // Now both nibbles are assembled
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assert_eq!(ram.ram_state, RamState::WaitLatency);
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}
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@ -271,8 +271,6 @@ fn create_system(system_type: &str, program_data: &[u8]) -> Result<ConfigurableS
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}
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fn run_system_demo(system: ConfigurableSystem) {
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let start_time = Instant::now();
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// Display system information
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let info = system.get_system_info();
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println!("System: {} - {}", info.name, info.description);
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