jan/rusty_emu
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

fix: address latching timing and cleanup debug code

Browse source
This commit is contained in:
Jan-Peter von Hunnius 2026-02-25 11:55:16 +01:00
parent aae374b713
commit 1cf2cd6e2b
6 changed files with 1102 additions and 265 deletions
Download patch file Download diff file Expand all files Collapse all files

38
src/components/memory/intel_4002.rs
View file

@ -486,10 +486,6 @@ impl Intel4002 {
/// Hardware: Φ2 high = Peripherals drive bus with data
/// Focus: Data driving operations
fn handle_phi2_rising(&mut self) {
println!(
"DEBUG: [RAM] Φ2 rising edge detected, current state: {:?}",
self.state_machine.get_state()
);
// Execute current state logic
self.execute_state_machine();
}
@ -499,10 +495,6 @@ impl Intel4002 {
/// Data is held on bus during Φ2 high, tri-stated when Φ2 falls
/// Focus: Clean up and return to idle state
fn handle_phi2_falling(&mut self) {
println!(
"DEBUG: [RAM] Φ2 falling edge detected, current state: {:?}",
self.state_machine.get_state()
);
match self.state_machine.get_state() {
Intel400xUnifiedState::ReadData
| Intel400xUnifiedState::WriteData
@ -532,10 +524,6 @@ impl Intel4002 {
/// Handle address nibble latching during address phase
/// Hardware: CPU provides 8-bit address as two 4-bit nibbles
fn handle_address_latching(&mut self) {
println!(
"DEBUG: handle_address_latching called, current state: {:?}",
self.state_machine.current_state
);
// Use common address latching functionality
let nibble = self.read_data_bus() & 0x0F; // Only 4 bits are valid for address nibbles
@ -551,21 +539,12 @@ impl Intel4002 {
if self.state_machine.is_full_address_ready() {
let address = self.state_machine.get_full_address().unwrap_or(0) as u8;
if let Some(data) = self.read_ram(address) {
println!(
"DEBUG: [RAM] Reading 0x{:02X} from address 0x{:02X} onto bus",
data, address
);
self.write_data_bus(data);
self.last_address = address as u16;
} else {
println!(
"DEBUG: [RAM] Invalid address 0x{:02X}, tri-stating bus",
address
);
self.tri_state_data_bus();
}
} else {
println!("DEBUG: [RAM] Address not ready, tri-stating bus");
self.tri_state_data_bus();
}
}
@ -576,27 +555,15 @@ impl Intel4002 {
if self.state_machine.is_full_address_ready() {
let address = self.state_machine.get_full_address().unwrap_or(0) as u8;
let data = self.read_data_bus();
println!(
"DEBUG: [RAM] Writing 0x{:02X} from bus to address 0x{:02X}",
data, address
);
if let Err(e) = self.write_ram(address, data) {
println!("DEBUG: [RAM] Write error: {}", e);
} else {
if self.write_ram(address, data).is_ok() {
self.last_address = address as u16;
}
} else {
println!("DEBUG: [RAM] Address not ready, ignoring write");
}
}
/// Handle status character output operation
/// Hardware: RAM drives status character pins with current status
fn handle_status_output(&mut self) {
println!(
"DEBUG: [RAM] Outputting status character 0x{:02X}",
self.status_character
);
self.drive_status_character();
}
@ -680,9 +647,7 @@ impl Component for Intel4002 {
/// Main update cycle - handles clock edge detection and operation dispatch
/// Hardware: Responds to Φ1 and Φ2 clock edges from CPU
fn update(&mut self) {
println!("DEBUG: Update called");
if !self.is_running() {
println!("DEBUG: Component not running, returning");
return;
}
// Handle both rising and falling edges for proper two-phase operation
@ -700,7 +665,6 @@ impl Component for Intel4002 {
let mut events = Vec::new();
if phi1_rising {
println!("DEBUG: phi1_rising detected");
events.push(Intel400xEvent::ClockPhi1Rising);
}