refactor: clean up test suite and apply code formatting
Remove redundant/obsolete tests from intel_400x_tests.rs, retaining core test coverage for Intel400x common functionality. Apply rustfmt formatting to intel_4002.rs and state machine test files. Changes: - Remove ~40 redundant test functions from intel_400x_tests.rs - Apply rustfmt formatting to intel_4002.rs - Fix import formatting in state machine tests - Clean up trailing whitespace
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4 changed files with 62 additions and 5898 deletions
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@ -9,7 +9,9 @@ use std::thread;
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use std::time::Duration;
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use rusty_emu::component::Component;
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use rusty_emu::components::common::intel_400x::{Intel400xTimingState, Intel400xUnifiedState, TimingState};
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use rusty_emu::components::common::intel_400x::{
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Intel400xTimingState, Intel400xUnifiedState, TimingState,
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};
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use rusty_emu::components::memory::intel_4002::{Intel4002, PendingOperation};
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use rusty_emu::pin::PinValue;
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@ -192,13 +194,13 @@ fn test_ram_read_state_progression() {
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// Manually transition to AddressPhase (simulating chip select)
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ram.set_state_for_test(Intel400xUnifiedState::AddressPhase);
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// Set address high nibble (0x0) on data bus
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set_data_bus(&ram, 0x0);
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// Generate Φ1 rising edge (no latching yet, data may not be stable)
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generate_clock_edge(&mut ram, true, false);
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// Generate Φ1 falling edge - address latching happens here (data is now stable)
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generate_clock_edge(&mut ram, false, false);
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@ -215,7 +217,7 @@ fn test_ram_read_state_progression() {
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// Generate Φ1 rising edge (no latching yet)
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generate_clock_edge(&mut ram, true, false);
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// Generate Φ1 falling edge - low nibble latching happens here
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generate_clock_edge(&mut ram, false, false);
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@ -229,7 +231,7 @@ fn test_ram_read_state_progression() {
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// Wait for latency to elapse (with 1ns access time, it should elapse immediately)
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std::thread::sleep(std::time::Duration::from_millis(1));
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// Generate Φ2 rising edge to trigger latency check and data driving
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generate_clock_edge(&mut ram, false, true);
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@ -239,7 +241,7 @@ fn test_ram_read_state_progression() {
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// Clear data bus drivers to prepare for reading
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clear_data_bus_drivers(&ram);
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// Execute state logic to drive data
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ram.update();
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@ -307,7 +309,7 @@ fn test_ram_write_state_progression() {
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// Generate Φ1 rising edge (no latching yet)
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generate_clock_edge(&mut ram, true, false);
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// Generate Φ1 falling edge - address latching happens here
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generate_clock_edge(&mut ram, false, false);
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@ -324,7 +326,7 @@ fn test_ram_write_state_progression() {
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// Generate Φ1 rising edge (no latching yet)
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generate_clock_edge(&mut ram, true, false);
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// Generate Φ1 falling edge - low nibble latching happens here
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generate_clock_edge(&mut ram, false, false);
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@ -392,7 +394,7 @@ fn test_output_port_state_progression() {
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// Generate Φ1 rising edge (no latching yet)
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generate_clock_edge(&mut ram, true, false);
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// Generate Φ1 falling edge - address latching happens here
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generate_clock_edge(&mut ram, false, false);
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@ -409,7 +411,7 @@ fn test_output_port_state_progression() {
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// Generate Φ1 rising edge (no latching yet)
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generate_clock_edge(&mut ram, true, false);
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// Generate Φ1 falling edge - low nibble latching happens here
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generate_clock_edge(&mut ram, false, false);
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@ -487,16 +489,19 @@ fn test_reset_functionality() {
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// Manually transition to AddressPhase and set up some state
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ram.set_state_for_test(Intel400xUnifiedState::AddressPhase);
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set_data_bus(&ram, 0x0);
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// Generate Φ1 rising edge (no latching yet)
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generate_clock_edge(&mut ram, true, false);
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// Generate Φ1 falling edge - address latching happens here
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generate_clock_edge(&mut ram, false, false);
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// Should have latched high nibble
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assert_eq!(ram.get_address_high_nibble(), Some(0x0));
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println!("Before reset: high_nibble={:?}", ram.get_address_high_nibble());
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println!(
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"Before reset: high_nibble={:?}",
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ram.get_address_high_nibble()
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);
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// Assert RESET (active low)
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let reset_pin = ram.get_pin("RESET").unwrap();
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@ -556,28 +561,49 @@ fn test_complete_state_machine_progression() {
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println!("Test 2: RAM Write Operation");
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ram.set_pending_operation(PendingOperation::Write);
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ram.set_state_for_test(Intel400xUnifiedState::AddressPhase);
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println!("Test 2: After set_state_for_test - nibbles: high={:?}, low={:?}",
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ram.get_address_high_nibble(), ram.get_address_low_nibble());
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println!(
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"Test 2: After set_state_for_test - nibbles: high={:?}, low={:?}",
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ram.get_address_high_nibble(),
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ram.get_address_low_nibble()
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);
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set_data_bus(&ram, 0x0);
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generate_clock_edge(&mut ram, true, false); // Φ1 rising (no latching yet)
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generate_clock_edge(&mut ram, false, false); // Φ1 falling - latch high nibble
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println!("Test 2: After first Φ1 falling - nibbles: high={:?}, low={:?}",
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ram.get_address_high_nibble(), ram.get_address_low_nibble());
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println!(
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"Test 2: After first Φ1 falling - nibbles: high={:?}, low={:?}",
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ram.get_address_high_nibble(),
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ram.get_address_low_nibble()
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);
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set_data_bus(&ram, 0x2);
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generate_clock_edge(&mut ram, true, false); // Φ1 rising (no latching yet)
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generate_clock_edge(&mut ram, false, false); // Φ1 falling - latch low nibble
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println!("Test 2: After second Φ1 falling - nibbles: high={:?}, low={:?}, full_address_ready={}",
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ram.get_address_high_nibble(), ram.get_address_low_nibble(),
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ram.get_full_address_ready());
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println!(
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"Test 2: After second Φ1 falling - nibbles: high={:?}, low={:?}, full_address_ready={}",
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ram.get_address_high_nibble(),
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ram.get_address_low_nibble(),
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ram.get_full_address_ready()
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);
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set_data_bus(&ram, 0x0F);
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println!("Test 2: Data bus set to 0x0F");
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std::thread::sleep(std::time::Duration::from_millis(1)); // Wait for latency
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println!("Test 2: Before Φ2 rising - state={:?}", ram.get_timing_state());
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println!(
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"Test 2: Before Φ2 rising - state={:?}",
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ram.get_timing_state()
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);
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generate_clock_edge(&mut ram, false, true); // Φ2 rising - write data
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println!("Test 2: After Φ2 rising - state={:?}", ram.get_timing_state());
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println!(
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"Test 2: After Φ2 rising - state={:?}",
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ram.get_timing_state()
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);
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generate_clock_edge(&mut ram, false, false); // Φ2 falling - return to idle
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println!("Test 2: After Φ2 falling - state={:?}", ram.get_timing_state());
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println!("Test 2: RAM[0x02]={:02X}, expected=0x0F", ram.read_ram(0x02).unwrap());
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println!(
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"Test 2: After Φ2 falling - state={:?}",
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ram.get_timing_state()
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);
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println!(
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"Test 2: RAM[0x02]={:02X}, expected=0x0F",
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ram.read_ram(0x02).unwrap()
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);
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assert_eq!(ram.get_timing_state(), TimingState::Idle);
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assert_eq!(ram.read_ram(0x02).unwrap(), 0x0F);
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println!("✅ RAM Write Operation completed");
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