refactor: clean up test suite and apply code formatting

Remove redundant/obsolete tests from intel_400x_tests.rs, retaining core test coverage for Intel400x common functionality. Apply rustfmt formatting to intel_4002.rs and state machine test files.

Changes:

- Remove ~40 redundant test functions from intel_400x_tests.rs

- Apply rustfmt formatting to intel_4002.rs

- Fix import formatting in state machine tests

- Clean up trailing whitespace

src/components/memory/intel_4002.rs

@@ -435,7 +435,8 @@ impl Intel4002 {
             if let Ok(pin) = self.base.get_pin(&format!("D{}", i)) {
                 if let Ok(mut pin_guard) = pin.lock() {
                     // Use the same driver name as write_data_bus() to properly tri-state
-                    pin_guard.set_driver(Some(format!("{}_DATA", self.base.name())), PinValue::HighZ);
+                    pin_guard
+                        .set_driver(Some(format!("{}_DATA", self.base.name())), PinValue::HighZ);
                 }
             }
         }
@@ -621,7 +622,7 @@ impl Intel4002 {
         if self.state_machine.is_full_address_ready() {
             let address = self.state_machine.get_full_address().unwrap_or(0) as u8;
             let data = self.read_data_bus();
-            
+
             // Determine which output port based on address
             // Output ports are at addresses 0x14-0x17 (port 0-3)
             let port = match address {
@@ -631,7 +632,7 @@ impl Intel4002 {
                 0x17 => Some(3),
                 _ => None,
             };
-            
+
             if let Some(port_num) = port {
                 // Write to I/O port
                 let _ = self.write_io_port(port_num, data);

tests/intel_4002_state_machine_test.rs

@@ -9,7 +9,9 @@ use std::thread;
 use std::time::Duration;
 
 use rusty_emu::component::Component;
-use rusty_emu::components::common::intel_400x::{Intel400xTimingState, Intel400xUnifiedState, TimingState};
+use rusty_emu::components::common::intel_400x::{
+    Intel400xTimingState, Intel400xUnifiedState, TimingState,
+};
 use rusty_emu::components::memory::intel_4002::{Intel4002, PendingOperation};
 use rusty_emu::pin::PinValue;
 
@@ -192,13 +194,13 @@ fn test_ram_read_state_progression() {
 
     // Manually transition to AddressPhase (simulating chip select)
     ram.set_state_for_test(Intel400xUnifiedState::AddressPhase);
-    
+
     // Set address high nibble (0x0) on data bus
     set_data_bus(&ram, 0x0);
 
     // Generate Φ1 rising edge (no latching yet, data may not be stable)
     generate_clock_edge(&mut ram, true, false);
-    
+
     // Generate Φ1 falling edge - address latching happens here (data is now stable)
     generate_clock_edge(&mut ram, false, false);
 
@@ -215,7 +217,7 @@ fn test_ram_read_state_progression() {
 
     // Generate Φ1 rising edge (no latching yet)
     generate_clock_edge(&mut ram, true, false);
-    
+
     // Generate Φ1 falling edge - low nibble latching happens here
     generate_clock_edge(&mut ram, false, false);
 
@@ -229,7 +231,7 @@ fn test_ram_read_state_progression() {
 
     // Wait for latency to elapse (with 1ns access time, it should elapse immediately)
     std::thread::sleep(std::time::Duration::from_millis(1));
-    
+
     // Generate Φ2 rising edge to trigger latency check and data driving
     generate_clock_edge(&mut ram, false, true);
 
@@ -239,7 +241,7 @@ fn test_ram_read_state_progression() {
 
     // Clear data bus drivers to prepare for reading
     clear_data_bus_drivers(&ram);
-    
+
     // Execute state logic to drive data
     ram.update();
 
@@ -307,7 +309,7 @@ fn test_ram_write_state_progression() {
 
     // Generate Φ1 rising edge (no latching yet)
     generate_clock_edge(&mut ram, true, false);
-    
+
     // Generate Φ1 falling edge - address latching happens here
     generate_clock_edge(&mut ram, false, false);
 
@@ -324,7 +326,7 @@ fn test_ram_write_state_progression() {
 
     // Generate Φ1 rising edge (no latching yet)
     generate_clock_edge(&mut ram, true, false);
-    
+
     // Generate Φ1 falling edge - low nibble latching happens here
     generate_clock_edge(&mut ram, false, false);
 
@@ -392,7 +394,7 @@ fn test_output_port_state_progression() {
 
     // Generate Φ1 rising edge (no latching yet)
     generate_clock_edge(&mut ram, true, false);
-    
+
     // Generate Φ1 falling edge - address latching happens here
     generate_clock_edge(&mut ram, false, false);
 
@@ -409,7 +411,7 @@ fn test_output_port_state_progression() {
 
     // Generate Φ1 rising edge (no latching yet)
     generate_clock_edge(&mut ram, true, false);
-    
+
     // Generate Φ1 falling edge - low nibble latching happens here
     generate_clock_edge(&mut ram, false, false);
 
@@ -487,16 +489,19 @@ fn test_reset_functionality() {
     // Manually transition to AddressPhase and set up some state
     ram.set_state_for_test(Intel400xUnifiedState::AddressPhase);
     set_data_bus(&ram, 0x0);
-    
+
     // Generate Φ1 rising edge (no latching yet)
     generate_clock_edge(&mut ram, true, false);
-    
+
     // Generate Φ1 falling edge - address latching happens here
     generate_clock_edge(&mut ram, false, false);
 
     // Should have latched high nibble
     assert_eq!(ram.get_address_high_nibble(), Some(0x0));
-    println!("Before reset: high_nibble={:?}", ram.get_address_high_nibble());
+    println!(
+        "Before reset: high_nibble={:?}",
+        ram.get_address_high_nibble()
+    );
 
     // Assert RESET (active low)
     let reset_pin = ram.get_pin("RESET").unwrap();
@@ -556,28 +561,49 @@ fn test_complete_state_machine_progression() {
     println!("Test 2: RAM Write Operation");
     ram.set_pending_operation(PendingOperation::Write);
     ram.set_state_for_test(Intel400xUnifiedState::AddressPhase);
-    println!("Test 2: After set_state_for_test - nibbles: high={:?}, low={:?}",
-             ram.get_address_high_nibble(), ram.get_address_low_nibble());
+    println!(
+        "Test 2: After set_state_for_test - nibbles: high={:?}, low={:?}",
+        ram.get_address_high_nibble(),
+        ram.get_address_low_nibble()
+    );
     set_data_bus(&ram, 0x0);
     generate_clock_edge(&mut ram, true, false); // Φ1 rising (no latching yet)
     generate_clock_edge(&mut ram, false, false); // Φ1 falling - latch high nibble
-    println!("Test 2: After first Φ1 falling - nibbles: high={:?}, low={:?}",
-             ram.get_address_high_nibble(), ram.get_address_low_nibble());
+    println!(
+        "Test 2: After first Φ1 falling - nibbles: high={:?}, low={:?}",
+        ram.get_address_high_nibble(),
+        ram.get_address_low_nibble()
+    );
     set_data_bus(&ram, 0x2);
     generate_clock_edge(&mut ram, true, false); // Φ1 rising (no latching yet)
     generate_clock_edge(&mut ram, false, false); // Φ1 falling - latch low nibble
-    println!("Test 2: After second Φ1 falling - nibbles: high={:?}, low={:?}, full_address_ready={}",
-             ram.get_address_high_nibble(), ram.get_address_low_nibble(),
-             ram.get_full_address_ready());
+    println!(
+        "Test 2: After second Φ1 falling - nibbles: high={:?}, low={:?}, full_address_ready={}",
+        ram.get_address_high_nibble(),
+        ram.get_address_low_nibble(),
+        ram.get_full_address_ready()
+    );
     set_data_bus(&ram, 0x0F);
     println!("Test 2: Data bus set to 0x0F");
     std::thread::sleep(std::time::Duration::from_millis(1)); // Wait for latency
-    println!("Test 2: Before Φ2 rising - state={:?}", ram.get_timing_state());
+    println!(
+        "Test 2: Before Φ2 rising - state={:?}",
+        ram.get_timing_state()
+    );
     generate_clock_edge(&mut ram, false, true); // Φ2 rising - write data
-    println!("Test 2: After Φ2 rising - state={:?}", ram.get_timing_state());
+    println!(
+        "Test 2: After Φ2 rising - state={:?}",
+        ram.get_timing_state()
+    );
     generate_clock_edge(&mut ram, false, false); // Φ2 falling - return to idle
-    println!("Test 2: After Φ2 falling - state={:?}", ram.get_timing_state());
-    println!("Test 2: RAM[0x02]={:02X}, expected=0x0F", ram.read_ram(0x02).unwrap());
+    println!(
+        "Test 2: After Φ2 falling - state={:?}",
+        ram.get_timing_state()
+    );
+    println!(
+        "Test 2: RAM[0x02]={:02X}, expected=0x0F",
+        ram.read_ram(0x02).unwrap()
+    );
     assert_eq!(ram.get_timing_state(), TimingState::Idle);
     assert_eq!(ram.read_ram(0x02).unwrap(), 0x0F);
     println!("✅ RAM Write Operation completed");

tests/intel_4003_state_machine_test.rs

@@ -131,7 +131,10 @@ fn test_intel_4003_state_machine_progression() {
     // The shift register operation requires proper state machine transitions.
     // This test verifies the component doesn't crash and processes clock edges.
     // Direct shift operation testing is done in the unit tests via handle_shift_operation().
-    println!("Shift register state after clock cycles: 0x{:03X}", shift_reg_value);
+    println!(
+        "Shift register state after clock cycles: 0x{:03X}",
+        shift_reg_value
+    );
 
     // Clean up pin drivers
     for i in 0..4 {