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Fix for last ram bank

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Jan-Peter von Hunnius 2025-09-24 16:50:20 +02:00
parent cb98a9b712
commit 3c85ed2b00
1 changed files with 7 additions and 2 deletions
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9
src/components/memory/intel_4002.rs
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@ -410,10 +410,12 @@ impl Intel4002 {
let start = (bank * 16) as usize; let start = (bank * 16) as usize;
let end = start + 16; let end = start + 16;
if end <= 40 { if end < 40 {
self.memory[start..end].to_vec() self.memory[start..end].to_vec()
} else { } else if start > 40 {
Vec::new() Vec::new()
} else {
self.memory[start..40].to_vec()
} }
} }
} }
@ -478,12 +480,15 @@ mod tests {
ram.write_ram(32, 0x03).unwrap(); // Bank 2 ram.write_ram(32, 0x03).unwrap(); // Bank 2
let bank0 = ram.get_ram_bank(0); let bank0 = ram.get_ram_bank(0);
assert_eq!(bank0.len(), 16);
assert_eq!(bank0[0], 0x01); assert_eq!(bank0[0], 0x01);
let bank1 = ram.get_ram_bank(1); let bank1 = ram.get_ram_bank(1);
assert_eq!(bank1.len(), 16);
assert_eq!(bank1[0], 0x02); assert_eq!(bank1[0], 0x02);
let bank2 = ram.get_ram_bank(2); let bank2 = ram.get_ram_bank(2);
assert_eq!(bank2.len(), 8);
assert_eq!(bank2[0], 0x03); assert_eq!(bank2[0], 0x03);
} }