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feat: migrate to parking_lot mutex and add system control architecture

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This commit is contained in:
Jan-Peter von Hunnius 2026-02-28 18:27:27 +01:00
parent 14060e15e5
commit 54144d10e9
29 changed files with 2387 additions and 1130 deletions
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100
tests/intel_4001_state_machine_test.rs
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@ -38,8 +38,8 @@ fn test_intel_4001_state_machine_progression() {
// Initialize clock pins to Low
{
let mut phi1_guard = phi1_pin.lock().unwrap();
let mut phi2_guard = phi2_pin.lock().unwrap();
let mut phi1_guard = phi1_pin.lock();
let mut phi2_guard = phi2_pin.lock();
phi1_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
phi2_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
}
@ -47,10 +47,10 @@ fn test_intel_4001_state_machine_progression() {
// Initialize control pins
// Note: RESET is active LOW, so set it to High to ensure component is not in reset
{
let mut sync_guard = sync_pin.lock().unwrap();
let mut cm_guard = cm_pin.lock().unwrap();
let mut ci_guard = ci_pin.lock().unwrap();
let mut reset_guard = reset_pin.lock().unwrap();
let mut sync_guard = sync_pin.lock();
let mut cm_guard = cm_pin.lock();
let mut ci_guard = ci_pin.lock();
let mut reset_guard = reset_pin.lock();
sync_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
cm_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
ci_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
@ -59,10 +59,10 @@ fn test_intel_4001_state_machine_progression() {
// Initialize data pins to Low
{
let mut d0_guard = d0_pin.lock().unwrap();
let mut d1_guard = d1_pin.lock().unwrap();
let mut d2_guard = d2_pin.lock().unwrap();
let mut d3_guard = d3_pin.lock().unwrap();
let mut d0_guard = d0_pin.lock();
let mut d1_guard = d1_pin.lock();
let mut d2_guard = d2_pin.lock();
let mut d3_guard = d3_pin.lock();
d0_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
d1_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
d2_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
@ -78,9 +78,9 @@ fn test_intel_4001_state_machine_progression() {
// Set up memory read operation: SYNC=1, CM=1, CI=0 (memory access)
{
let mut sync_guard = sync_pin.lock().unwrap();
let mut cm_guard = cm_pin.lock().unwrap();
let mut ci_guard = ci_pin.lock().unwrap();
let mut sync_guard = sync_pin.lock();
let mut cm_guard = cm_pin.lock();
let mut ci_guard = ci_pin.lock();
sync_guard.set_driver(Some("TEST".to_string()), PinValue::High);
cm_guard.set_driver(Some("TEST".to_string()), PinValue::High);
ci_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Memory access
@ -88,10 +88,10 @@ fn test_intel_4001_state_machine_progression() {
// Set up address high nibble (0x1 for address 0x12)
{
let mut d0_guard = d0_pin.lock().unwrap();
let mut d1_guard = d1_pin.lock().unwrap();
let mut d2_guard = d2_pin.lock().unwrap();
let mut d3_guard = d3_pin.lock().unwrap();
let mut d0_guard = d0_pin.lock();
let mut d1_guard = d1_pin.lock();
let mut d2_guard = d2_pin.lock();
let mut d3_guard = d3_pin.lock();
// 0x1 = 0001 (D0=1, D1=0, D2=0, D3=0)
d0_guard.set_driver(Some("TEST".to_string()), PinValue::High);
d1_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
@ -104,7 +104,7 @@ fn test_intel_4001_state_machine_progression() {
// Trigger Φ1 rising edge to start memory operation and latch high nibble
{
let mut phi1_guard = phi1_pin.lock().unwrap();
let mut phi1_guard = phi1_pin.lock();
phi1_guard.set_driver(Some("TEST".to_string()), PinValue::High);
}
@ -120,7 +120,7 @@ fn test_intel_4001_state_machine_progression() {
// Reset Φ1 to Low
{
let mut phi1_guard = phi1_pin.lock().unwrap();
let mut phi1_guard = phi1_pin.lock();
phi1_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
}
@ -129,10 +129,10 @@ fn test_intel_4001_state_machine_progression() {
// Set up address low nibble (0x2 for address 0x12)
{
let mut d0_guard = d0_pin.lock().unwrap();
let mut d1_guard = d1_pin.lock().unwrap();
let mut d2_guard = d2_pin.lock().unwrap();
let mut d3_guard = d3_pin.lock().unwrap();
let mut d0_guard = d0_pin.lock();
let mut d1_guard = d1_pin.lock();
let mut d2_guard = d2_pin.lock();
let mut d3_guard = d3_pin.lock();
// 0x2 = 0010 (D0=0, D1=1, D2=0, D3=0)
d0_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
d1_guard.set_driver(Some("TEST".to_string()), PinValue::High);
@ -146,7 +146,7 @@ fn test_intel_4001_state_machine_progression() {
// Trigger Φ1 rising edge again - ROM should stay in AddressPhase
// (address nibbles are latched on Φ1 falling edge, not rising)
{
let mut phi1_guard = phi1_pin.lock().unwrap();
let mut phi1_guard = phi1_pin.lock();
phi1_guard.set_driver(Some("TEST".to_string()), PinValue::High);
}
@ -166,7 +166,7 @@ fn test_intel_4001_state_machine_progression() {
// Reset Φ1 to Low to trigger falling edge - this is when low nibble is latched
{
let mut phi1_guard = phi1_pin.lock().unwrap();
let mut phi1_guard = phi1_pin.lock();
phi1_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
}
@ -189,10 +189,10 @@ fn test_intel_4001_state_machine_progression() {
// Remove test drivers from data pins to allow ROM to drive bus
{
let mut d0_guard = d0_pin.lock().unwrap();
let mut d1_guard = d1_pin.lock().unwrap();
let mut d2_guard = d2_pin.lock().unwrap();
let mut d3_guard = d3_pin.lock().unwrap();
let mut d0_guard = d0_pin.lock();
let mut d1_guard = d1_pin.lock();
let mut d2_guard = d2_pin.lock();
let mut d3_guard = d3_pin.lock();
d0_guard.remove_driver("TEST");
d1_guard.remove_driver("TEST");
d2_guard.remove_driver("TEST");
@ -203,7 +203,7 @@ fn test_intel_4001_state_machine_progression() {
if rom.get_timing_state() == TimingState::WaitLatency {
// Trigger Φ2 rising edge
{
let mut phi2_guard = phi2_pin.lock().unwrap();
let mut phi2_guard = phi2_pin.lock();
phi2_guard.set_driver(Some("TEST".to_string()), PinValue::High);
}
@ -221,14 +221,14 @@ fn test_intel_4001_state_machine_progression() {
// Verify data is being driven on the bus
// Data 0xAB has low nibble 0xB = 1011 (D0=1, D1=1, D2=0, D3=1)
// Note: Due to bit ordering, D0 should be High, D1 should be High, D2 should be Low, D3 should be High
assert_eq!(d0_pin.lock().unwrap().read(), PinValue::High);
assert_eq!(d1_pin.lock().unwrap().read(), PinValue::High);
assert_eq!(d2_pin.lock().unwrap().read(), PinValue::Low);
assert_eq!(d3_pin.lock().unwrap().read(), PinValue::High);
assert_eq!(d0_pin.lock().read(), PinValue::High);
assert_eq!(d1_pin.lock().read(), PinValue::High);
assert_eq!(d2_pin.lock().read(), PinValue::Low);
assert_eq!(d3_pin.lock().read(), PinValue::High);
// Reset Φ2 to Low
{
let mut phi2_guard = phi2_pin.lock().unwrap();
let mut phi2_guard = phi2_pin.lock();
phi2_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
}
@ -240,10 +240,10 @@ fn test_intel_4001_state_machine_progression() {
println!("Final state: {:?}", rom.get_timing_state());
// Verify data bus is tri-stated
assert_eq!(d0_pin.lock().unwrap().read(), PinValue::HighZ);
assert_eq!(d1_pin.lock().unwrap().read(), PinValue::HighZ);
assert_eq!(d2_pin.lock().unwrap().read(), PinValue::HighZ);
assert_eq!(d3_pin.lock().unwrap().read(), PinValue::HighZ);
assert_eq!(d0_pin.lock().read(), PinValue::HighZ);
assert_eq!(d1_pin.lock().read(), PinValue::HighZ);
assert_eq!(d2_pin.lock().read(), PinValue::HighZ);
assert_eq!(d3_pin.lock().read(), PinValue::HighZ);
}
/// Test to verify that unified state machine doesn't progress without proper control signals
@ -261,8 +261,8 @@ fn test_intel_4001_state_machine_no_progression_without_signals() {
// Initialize clock pins to Low
{
let mut phi1_guard = phi1_pin.lock().unwrap();
let mut phi2_guard = phi2_pin.lock().unwrap();
let mut phi1_guard = phi1_pin.lock();
let mut phi2_guard = phi2_pin.lock();
phi1_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
phi2_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
}
@ -275,7 +275,7 @@ fn test_intel_4001_state_machine_no_progression_without_signals() {
// Trigger clock edges without setting up control signals
{
let mut phi1_guard = phi1_pin.lock().unwrap();
let mut phi1_guard = phi1_pin.lock();
phi1_guard.set_driver(Some("TEST".to_string()), PinValue::High);
}
@ -287,7 +287,7 @@ fn test_intel_4001_state_machine_no_progression_without_signals() {
// Reset Φ1 to Low
{
let mut phi1_guard = phi1_pin.lock().unwrap();
let mut phi1_guard = phi1_pin.lock();
phi1_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
}
@ -296,7 +296,7 @@ fn test_intel_4001_state_machine_no_progression_without_signals() {
// Trigger Φ2 rising edge
{
let mut phi2_guard = phi2_pin.lock().unwrap();
let mut phi2_guard = phi2_pin.lock();
phi2_guard.set_driver(Some("TEST".to_string()), PinValue::High);
}
@ -325,7 +325,7 @@ fn test_intel_4001_state_machine_reset() {
// Initialize clock pins to Low
{
let mut phi1_guard = phi1_pin.lock().unwrap();
let mut phi1_guard = phi1_pin.lock();
phi1_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
}
@ -337,9 +337,9 @@ fn test_intel_4001_state_machine_reset() {
// Set up memory read operation: SYNC=1, CM=1, CI=0 (memory access)
{
let mut sync_guard = sync_pin.lock().unwrap();
let mut cm_guard = cm_pin.lock().unwrap();
let mut ci_guard = ci_pin.lock().unwrap();
let mut sync_guard = sync_pin.lock();
let mut cm_guard = cm_pin.lock();
let mut ci_guard = ci_pin.lock();
sync_guard.set_driver(Some("TEST".to_string()), PinValue::High);
cm_guard.set_driver(Some("TEST".to_string()), PinValue::High);
ci_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Memory access
@ -347,7 +347,7 @@ fn test_intel_4001_state_machine_reset() {
// Trigger Φ1 rising edge to start memory operation
{
let mut phi1_guard = phi1_pin.lock().unwrap();
let mut phi1_guard = phi1_pin.lock();
phi1_guard.set_driver(Some("TEST".to_string()), PinValue::High);
}
@ -359,7 +359,7 @@ fn test_intel_4001_state_machine_reset() {
// Assert RESET (active LOW - set to Low to trigger reset)
{
let mut reset_guard = reset_pin.lock().unwrap();
let mut reset_guard = reset_pin.lock();
reset_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
}