Unified the 400x state machine for address latching
Fixed timing issues
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README.md
96
README.md
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@ -18,31 +18,35 @@ provides:
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### System Components
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The emulator implements the complete Intel MCS-4 system:
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The emulator implements the complete Intel MCS-4 system using a unified state machine architecture:
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```
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Intel 4004 CPU (4-bit microprocessor)
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├── 16 × 4-bit register file
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├── ALU with carry/borrow logic
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├── Program counter and stack
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└── Two-phase clock interface
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├── Two-phase clock interface
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└── Unified state machine (FetchInstruction, ExecuteInstruction states)
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Intel 4001 ROM (256 bytes with I/O)
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├── Mask-programmable ROM storage
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├── 4-bit I/O port interface
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├── Two-phase addressing
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└── 500ns typical access time
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├── 500ns typical access time
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└── Unified state machine (Idle, AddressPhase, WaitLatency, DriveData states)
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Intel 4002 RAM (320 bits with output)
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├── 80 × 4-bit character storage
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├── 4-bit output port
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├── Refresh circuitry
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└── Banked memory organization
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├── Banked memory organization
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└── Unified state machine (Idle, AddressPhase, WaitLatency, ReadData, WriteData, OutputPort states)
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Intel 4003 Shift Register (10-bit serial I/O)
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├── 10-bit static shift register
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├── Serial input/output
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└── 200ns access time
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├── 200ns access time
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└── Unified state machine (Idle, ShiftData, LoadData states)
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```
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### Key Features
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@ -55,6 +59,64 @@ Intel 4003 Shift Register (10-bit serial I/O)
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- **Graphical User Interface**: Modern desktop application with real-time monitoring
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- **Interactive Console**: Terminal-based interface with live system monitoring
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## Unified Intel 400x State Machine
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The emulator implements a generalized state machine architecture for all Intel 400x series components, replacing individual chip state machines with a unified framework. This approach provides consistency, maintainability, and extensibility across all supported components.
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### Architecture Overview
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The unified state machine is built around several key components:
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- **Intel400xComponentType**: Enumeration identifying specific Intel 400x chip type (4001 ROM, 4002 RAM, 4003 I/O Port, 4004 CPU)
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- **Intel400xUnifiedState**: Comprehensive state enumeration covering all possible states for any Intel 400x component
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- **Intel400xEvent**: Event system that triggers state transitions (clock edges, control signals, etc.)
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- **Intel400xStateMachine**: Core state machine engine handling transitions and timing
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- **Intel400xComponentBehavior**: Trait defining component-specific behavior while using the common framework
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### Supported Components
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The unified state machine supports all major Intel 400x components:
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#### Intel 4001 ROM (256 bytes with I/O)
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- **States**: Idle, AddressPhase, WaitLatency, DriveData
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- **Functionality**: Mask-programmable ROM storage with 4-bit I/O port interface
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- **Access Time**: 500ns typical access time
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- **Special Features**: Two-phase addressing, I/O port operations
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#### Intel 4002 RAM (320 bits with output)
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- **States**: Idle, AddressPhase, WaitLatency, ReadData, WriteData, OutputPort
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- **Functionality**: 80 × 4-bit character storage with 4-bit output port
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- **Access Time**: 500ns typical access time
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- **Special Features**: Banked memory organization, refresh circuitry, status output
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#### Intel 4003 Shift Register (10-bit serial I/O)
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- **States**: Idle, ShiftData, LoadData
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- **Functionality**: 10-bit static shift register for I/O expansion
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- **Access Time**: 200ns access time (faster than memory components)
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- **Special Features**: Ignores address transmission, operates in shift mode only
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### Benefits of the Unified Approach
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1. **Code Reuse**: Common state transition logic is shared across all components, reducing duplication
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2. **Consistency**: All components follow the same timing patterns and state conventions
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3. **Maintainability**: Changes to common behavior only need to be made in one place
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4. **Extensibility**: New chip types can be added by implementing the Intel400xComponentBehavior trait
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5. **Testability**: The state machine can be tested independently of specific components
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6. **Type Safety**: Rust's type system ensures correct state transitions and prevents invalid states
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### Implementation Details
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The unified state machine handles the 4-bit multiplexed address/data bus used by the Intel 400x series:
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1. **Address Phase**: Components receive address information in two 4-bit phases (high nibble first, then low nibble)
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2. **Latency Wait**: After address latching, components wait for the required access time
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3. **Data Transfer**: Components either drive data onto the bus (read) or accept data (write)
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4. **Return to Idle**: Operations complete and components return to the idle state
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Each component implements the `Intel400xComponentBehavior` trait to provide its specific functionality while using the common state machine framework. This approach maintains the unique characteristics of each chip while ensuring consistent behavior across the system.
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For more detailed information about the unified state machine implementation, see the documentation in [`src/components/common/intel_400x.rs`](src/components/common/intel_400x.rs).
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## Project Structure
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```
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@ -144,9 +206,9 @@ cargo add egui eframe rfd
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```rust
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use rusty_emu::components::memory::intel_4001::Intel4001;
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use rusty_emu::components::common::intel_400x::TimingState;
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use rusty_emu::components::common::intel_400x::{Intel400xComponentBehavior, Intel400xUnifiedState};
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// Create a ROM component
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// Create a ROM component with unified state machine
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let mut rom = Intel4001::new("ROM1".to_string());
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// Load program data
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@ -155,6 +217,9 @@ rom.load_rom_data(program, 0) ?;
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// Use in simulation
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rom.update(); // Process one clock cycle
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// Components now use unified state machine internally
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// States: Idle -> AddressPhase -> WaitLatency -> DriveData -> Idle
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```
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### JSON Configuration System
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@ -466,7 +531,17 @@ The test suite demonstrates:
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- ✅ **Pin-Level Connection Management**: Automatic wiring of component interconnections
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- ✅ **Runtime System Selection**: Support for multiple system configurations
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### 2. Testability Demonstration
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### 2. Unified State Machine Architecture
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**Groundbreaking Component Framework:**
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- ✅ **Generalized State Machine**: Single framework for all Intel 400x components
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- ✅ **Intel400xComponentBehavior Trait**: Component-specific logic with common infrastructure
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- ✅ **Event-Driven Design**: Clean separation of state transitions and component behavior
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- ✅ **Type-Safe Implementation**: Rust's type system ensures correct state transitions
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- ✅ **Code Deduplication**: Eliminated duplicate state machine implementations
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### 3. Testability Demonstration
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**Answer to Original Question: CONFIRMED**
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@ -476,7 +551,7 @@ The test suite demonstrates:
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- ✅ **Deterministic behavior**: State machines have predictable outcomes
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- ✅ **Integration testing**: Real components work correctly with common traits
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### 3. Comprehensive Test Suite
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### 4. Comprehensive Test Suite
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- **416+ lines** of comprehensive test code
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- **Multiple testing strategies**: Unit, mock-based, property-based, integration
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@ -484,7 +559,7 @@ The test suite demonstrates:
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- **Working examples**: Demonstrates practical usage patterns
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- **System-level testing**: End-to-end verification of complete systems
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### 4. Clean Architecture
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### 5. Clean Architecture
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- **Trait-based design**: Enables code reuse and testing
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- **Separation of concerns**: Clear boundaries between components
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@ -501,6 +576,7 @@ The test suite demonstrates:
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- Intel 4004 CPU structure and instruction framework
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- Intel 4002 RAM implementation with refresh circuitry
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- Intel 4003 Shift Register implementation
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- **Unified state machine architecture for all Intel 400x components**
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- JSON-based system configuration architecture
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- Comprehensive test suite (416+ lines of tests)
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- Documentation system
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