feat: Add real-time data display for CPU registers, RAM, and ROM

This commit is contained in:
Jan-Peter von Hunnius 2026-02-26 19:36:59 +01:00
parent 3530ea5f28
commit 6636417d18
22 changed files with 1233 additions and 188 deletions

View file

@ -22,6 +22,8 @@ pub struct GuiState {
pub component_states: ComponentStates,
/// Memory state
pub memory_state: MemoryState,
/// ROM state
pub rom_state: RomState,
/// CPU register state
pub register_state: RegisterState,
/// Last error message
@ -54,6 +56,18 @@ pub struct MemoryState {
pub ram_contents: Vec<[u8; 4]>, // 4 banks of RAM data
pub selected_bank: usize,
pub selected_address: usize,
/// Display mode: true for hexadecimal, false for decimal
pub show_hex: bool,
}
/// ROM state for display
#[derive(Debug, Clone)]
pub struct RomState {
pub rom_contents: Vec<u8>,
pub selected_address: usize,
pub chip_name: String,
/// Display mode: true for hexadecimal, false for decimal
pub show_hex: bool,
}
/// CPU register state for display
@ -62,8 +76,10 @@ pub struct RegisterState {
pub accumulator: u8,
pub carry_flag: bool,
pub program_counter: u16,
pub index_registers: [u8; 16], // 16 index registers (R0-R15)
pub index_registers: [u8; 16], // 16 index registers (R0-R15) for Intel 4004
pub stack_pointer: u8,
/// Currently selected index register for detailed view (0-15)
pub selected_register: usize,
}
impl GuiState {
@ -84,6 +100,13 @@ impl GuiState {
ram_contents: vec![[0; 4]; 4], // Initialize 4 banks with 4 bytes each
selected_bank: 0,
selected_address: 0,
show_hex: true,
},
rom_state: RomState {
rom_contents: vec![0; 256], // Initialize with 256 bytes
selected_address: 0,
chip_name: String::new(),
show_hex: true,
},
register_state: RegisterState {
accumulator: 0,
@ -91,6 +114,7 @@ impl GuiState {
program_counter: 0,
index_registers: [0; 16],
stack_pointer: 0,
selected_register: 0,
},
last_error: None,
}
@ -110,6 +134,15 @@ impl GuiState {
// Update component states
self.update_component_states(&system_guard);
// Update CPU register state from real data
self.update_register_state(&system_guard);
// Update RAM state from real data
self.update_ram_state(&system_guard);
// Update ROM state from real data
self.update_rom_state(&system_guard);
// Update cycle count (simulate for now)
if self.system_running {
self.cycle_count += 1;
@ -146,6 +179,50 @@ impl GuiState {
});
}
/// Update CPU register state from real component data
fn update_register_state(&mut self, system: &ConfigurableSystem) {
if let Some(cpu_data) = system.get_cpu_register_data() {
self.register_state.accumulator = cpu_data.accumulator;
self.register_state.carry_flag = cpu_data.carry;
self.register_state.program_counter = cpu_data.program_counter;
self.register_state.stack_pointer = cpu_data.stack_pointer;
self.register_state
.index_registers
.copy_from_slice(&cpu_data.index_registers);
}
}
/// Update RAM state from real component data
fn update_ram_state(&mut self, system: &ConfigurableSystem) {
let ram_data = system.get_ram_data(4); // Get up to 4 rows per bank
if !ram_data.is_empty() {
// Take the first RAM chip's data
let (_, banks) = &ram_data[0];
// Convert bank data to our display format
self.memory_state.ram_contents.clear();
for bank in banks {
let mut row = [0u8; 4];
for (i, nibble) in bank.iter().take(4).enumerate() {
row[i] = *nibble;
}
self.memory_state.ram_contents.push(row);
}
}
}
/// Update ROM state from real component data
fn update_rom_state(&mut self, system: &ConfigurableSystem) {
let rom_data = system.get_rom_data(256); // Get up to 256 bytes
if !rom_data.is_empty() {
let (chip_name, data) = &rom_data[0];
self.rom_state.chip_name = chip_name.clone();
self.rom_state.rom_contents = data.clone();
}
}
/// Set an error message
pub fn set_error(&mut self, error: String) {
self.last_error = Some(error);