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feat: Add real-time data display for CPU registers, RAM, and ROM

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This commit is contained in:
Jan-Peter von Hunnius 2026-02-26 19:36:59 +01:00
parent 3530ea5f28
commit 6636417d18
22 changed files with 1233 additions and 188 deletions
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36
tests/intel_4002_state_machine_test.rs
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@ -49,42 +49,6 @@ fn wait_for_pin_settlement() {
thread::sleep(Duration::from_nanos(10)); // 10ns settlement time
}
/// Test helper to set control pins for RAM operation
/// RAM requires: SYNC=1, CM=1 (chip_select), CI=1 (io_select for RAM vs ROM)
fn setup_ram_operation(ram: &Intel4002, sync_high: bool, cm_high: bool) {
let sync_pin = ram.get_pin("SYNC").unwrap();
let cm_pin = ram.get_pin("CM").unwrap();
let ci_pin = ram.get_pin("CI").unwrap();
// Set control pins
{
let mut sync_guard = sync_pin.lock().unwrap();
let mut cm_guard = cm_pin.lock().unwrap();
let mut ci_guard = ci_pin.lock().unwrap();
sync_guard.set_driver(
Some("TEST".to_string()),
if sync_high {
PinValue::High
} else {
PinValue::Low
},
);
cm_guard.set_driver(
Some("TEST".to_string()),
if cm_high {
PinValue::High
} else {
PinValue::Low
},
);
// CI must be HIGH for RAM operations (distinguishes RAM from ROM)
ci_guard.set_driver(Some("TEST".to_string()), PinValue::High);
}
wait_for_pin_settlement();
}
/// Test helper to set data bus value
fn set_data_bus(ram: &Intel4002, value: u8) {
let nibble = value & 0x0F; // Only lower 4 bits