Fix Intel 4004 CPU instruction set and improve MCS-4 timing accuracy

Overhaul the Intel 4004 instruction set to match the real opcode map,
adding missing instructions (NOP, FIM, FIN, JIN, ISZ, KBP, DCL, WR0-3,
RD0-3) and refining two-byte instruction handling with proper M1/M2
data phases.  Rewrite the CPU fetch-execute cycle to correctly process
two-byte opcodes across separate clock cycles.

Improve Intel 4001 ROM timing with M1/M2 nibble phase tracking and an
A3 wait counter so the ROM drives data only when the CPU expects it.
Fix state-machine transition helpers in Intel 4002 and 4003 to capture
the old state before processing events, preventing incorrect exit/entry
callbacks.

Add non-propagating pin driver methods to prevent deadlocks caused by
bidirectional pin connections during signal propagation.

Add Fibonacci integration test and opcode fix plan document.
Update all README files to reflect the new instruction set.

README.md

@@ -26,7 +26,7 @@ Intel 4004 CPU (4-bit microprocessor)
 ├── ALU with carry/borrow logic
 ├── Program counter and stack
 ├── Two-phase clock interface
-└── Unified state machine (FetchInstruction, ExecuteInstruction states)
+└── Unified state machine (FetchByte1, FetchByte2, Execute states)
 
 Intel 4001 ROM (256 bytes with I/O)
 ├── Mask-programmable ROM storage
@@ -123,36 +123,48 @@ For more detailed information about the unified state machine implementation, se
 rusty_emu/
 ├── src/                    # Source code
 │   ├── lib.rs             # Library exports
-│   ├── main.rs            # Binary entry point with JSON configuration
+│   ├── main.rs            # Binary entry point with GUI, console, and JSON configuration
 │   ├── component.rs       # Core component traits
+│   ├── connection.rs      # Component interconnection system
 │   ├── pin.rs            # Pin and signal system
+│   ├── types.rs          # Common type definitions
 │   ├── system_config.rs   # JSON-based system configuration system
-│   ├── console.rs         # Interactive console interface
-│   ├── gui.rs            # Graphical user interface module
+│   ├── gui/              # Graphical user interface module
 │   │   ├── components.rs  # GUI component implementations
 │   │   ├── state.rs      # GUI state management
 │   │   └── mod.rs        # GUI module exports
-│   ├── components/        # Hardware components
-│   │   ├── common/       # Shared Intel 400x functionality
-│   │   ├── cpu/          # CPU implementations
-│   │   ├── memory/       # Memory components
-│   │   └── clock/       # Clock generation
-│   └── systems/          # System integration (legacy)
+│   └── components/        # Hardware components
+│       ├── common/       # Shared Intel 400x functionality
+│       ├── cpu/          # CPU implementations (Intel 4004, MOS 6502, WDC 65C02)
+│       ├── memory/       # Memory components (Intel 4001, 4002, 4003)
+│       └── clock/       # Clock generation
 ├── configs/               # JSON system configuration files
 │   ├── mcs4_basic.json   # Basic MCS-4 system configuration
-│   └── mcs4_max.json     # Fig.1 MCS-4 Max system configuration
+│   ├── mcs4_max.json     # Fig.1 MCS-4 Max system configuration
+│   ├── mcs4_io_demo.json # I/O demonstration configuration
+│   └── console_config.xml # Console interface configuration
 ├── programs/             # Binary program files
 │   ├── README.md        # Program documentation
-│   └── fibonacci.bin    # Example Fibonacci program
+│   ├── fibonacci.bin    # Example Fibonacci program
+│   └── fibonacci_output.bin # Fibonacci with output port visibility
 ├── tests/               # Comprehensive test suite
 │   ├── README.md       # Test documentation
 │   ├── lib.rs         # Test library
-│   ├── mocks.rs      # Mock implementations
 │   ├── intel_400x_tests.rs    # Common functionality tests
-│   ├── mock_based_tests.rs    # Mock-based tests
-│   ├── property_based_tests.rs # Property verification
-│   └── integration_tests.rs   # System integration tests
-└── docs/               # Documentation
+│   ├── intel_4001_state_machine_test.rs  # 4001 state machine tests
+│   ├── intel_4002_state_machine_test.rs  # 4002 state machine tests
+│   ├── intel_4003_state_machine_test.rs  # 4003 state machine tests
+│   ├── intel_4004_state_machine_test.rs  # 4004 state machine tests
+│   ├── integration_tests.rs   # System integration tests
+│   ├── json_integration_tests.rs # JSON config tests
+│   ├── simple_test.rs         # Core functionality demo
+│   ├── gui_tests.rs           # GUI component tests
+│   └── gui_integration_tests.rs # GUI integration tests
+├── plans/               # Design documents
+│   ├── intel_4004_opcode_fix.md # Opcode fix design document
+│   ├── codebase_analysis.md     # Codebase analysis
+│   └── system_control_architecture.md # System architecture
+└── CONSOLE_README.md    # Console interface documentation
 ```
 
 ## Quick Start
@@ -573,7 +585,13 @@ The test suite demonstrates:
 
 - Core component architecture with trait-based design
 - Intel 4001 ROM implementation with I/O ports
-- Intel 4004 CPU structure and instruction framework
+- **Intel 4004 CPU with complete instruction set (all 46 instructions)**
+- **Correct opcode decoding table per Intel 4004 datasheet**
+- **Two-byte instruction handling (FetchByte1→FetchByte2→Execute state machine)**
+- **I/O and RAM instructions fully implemented (WRM, WMP, WRR, WPM, WR0-WR3, SBM, RDM, RDR, ADM, RD0-RD3)**
+- **Accumulator group instructions (CLB, CLC, IAC, CMC, CMA, RAL, RAR, TCC, TCS, STC, DAA, KBP, DCL)**
+- **JCN condition decoding with correct bit-field (invert/ACC zero/carry/TEST pin)**
+- **SRC properly implemented using register pairs with src_address storage**
 - Intel 4002 RAM implementation with refresh circuitry
 - Intel 4003 Shift Register implementation
 - **Unified state machine architecture for all Intel 400x components**
@@ -588,7 +606,6 @@ The test suite demonstrates:
 
 ### 🚧 In Progress
 
-- Complete Intel 4004 instruction execution engine
 - System integration and timing verification
 - Performance optimization and benchmarking