Fix Intel 4004 CPU instruction set and improve MCS-4 timing accuracy

Overhaul the Intel 4004 instruction set to match the real opcode map,
adding missing instructions (NOP, FIM, FIN, JIN, ISZ, KBP, DCL, WR0-3,
RD0-3) and refining two-byte instruction handling with proper M1/M2
data phases.  Rewrite the CPU fetch-execute cycle to correctly process
two-byte opcodes across separate clock cycles.

Improve Intel 4001 ROM timing with M1/M2 nibble phase tracking and an
A3 wait counter so the ROM drives data only when the CPU expects it.
Fix state-machine transition helpers in Intel 4002 and 4003 to capture
the old state before processing events, preventing incorrect exit/entry
callbacks.

Add non-propagating pin driver methods to prevent deadlocks caused by
bidirectional pin connections during signal propagation.

Add Fibonacci integration test and opcode fix plan document.
Update all README files to reflect the new instruction set.
This commit is contained in:
Jan-Peter von Hunnius 2026-05-12 19:32:01 +02:00
parent 54144d10e9
commit 6a335a15d4
14 changed files with 4125 additions and 1062 deletions

View file

@ -67,14 +67,16 @@ MCS-4 programs are stored as raw binary data where each instruction is represent
## Program Development Tips
### Making Programs Visible
- **Use Output Ports:** Write results to output ports (0x14-0x17) for visibility
- **SRC Instruction:** Select output port with `SRC` before `WRM`
- **Use Output Ports:** Write results to output ports via `WRR` (ROM port) or `WMP` (RAM port) for visibility
- **SRC Instruction:** Select target chip/address with `SRC` before I/O operations
- **Real-time Output:** Numbers appear on output ports during execution
- **System Monitoring:** Watch RAM contents and output port states in real-time
### Example Output Port Usage
```asm
LDM 5 ; Load value 5
SRC 0 ; Select output port 0
WRM ; Write to output port 0 (now visible to user)
```
FIM R0, 0x05 ; Load register pair R0/R1 with address (R0=0, R1=5)
SRC R0 ; Send register control from R0/R1 — selects chip/port
WRM ; Write ACC to RAM main memory at selected address
```
> **Note**: `SRC` takes a register *pair* number (0-7), not a direct port number. The register pair contents form the 8-bit address used for I/O and RAM operations. See the Intel 4004 datasheet for details.