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Fix Intel 4004 CPU instruction set and improve MCS-4 timing accuracy

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Overhaul the Intel 4004 instruction set to match the real opcode map,
adding missing instructions (NOP, FIM, FIN, JIN, ISZ, KBP, DCL, WR0-3,
RD0-3) and refining two-byte instruction handling with proper M1/M2
data phases.  Rewrite the CPU fetch-execute cycle to correctly process
two-byte opcodes across separate clock cycles.

Improve Intel 4001 ROM timing with M1/M2 nibble phase tracking and an
A3 wait counter so the ROM drives data only when the CPU expects it.
Fix state-machine transition helpers in Intel 4002 and 4003 to capture
the old state before processing events, preventing incorrect exit/entry
callbacks.

Add non-propagating pin driver methods to prevent deadlocks caused by
bidirectional pin connections during signal propagation.

Add Fibonacci integration test and opcode fix plan document.
Update all README files to reflect the new instruction set.
This commit is contained in:
Jan-Peter von Hunnius 2026-05-12 19:32:01 +02:00
parent 54144d10e9
commit 6a335a15d4
14 changed files with 4125 additions and 1062 deletions
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7
src/components/common/README.md
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@ -74,8 +74,9 @@ pub enum Intel400xUnifiedState {
OutputPort, // Intel 4002 (RAM) specific
ShiftData, // Intel 4003 (Shift Register) specific
LoadData, // Intel 4003 (Shift Register) specific
FetchInstruction, // Intel 4004 (CPU) specific
ExecuteInstruction, // Intel 4004 (CPU) specific
FetchByte1, // Intel 4004 (CPU) specific — fetching first byte
FetchByte2, // Intel 4004 (CPU) specific — fetching second byte of 2-byte instruction
Execute, // Intel 4004 (CPU) specific — executing decoded instruction
}
```
@ -292,7 +293,7 @@ The unified state machine operates by:
- **Intel 4001 (ROM)**: Transitions to DriveData to provide read-only data
- **Intel 4002 (RAM)**: Transitions to ReadData, WriteData, or OutputPort based on operation
- **Intel 4003 (Shift Register)**: Ignores address transmission, goes directly to ShiftData
- **Intel 4004 (CPU)**: Uses FetchInstruction and ExecuteInstruction states
- **Intel 4004 (CPU)**: Uses FetchByte1, FetchByte2, and Execute states for instruction processing
## Timing Constants