Created factory for system creation.
Systems are now defined in JSON rather than hard-coded
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# Hardware Components
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This directory contains implementations of various hardware components used in the Intel 4004 microprocessor system and other architectures.
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This directory contains implementations of various hardware components used in the Intel 4004 microprocessor system and
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other architectures.
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## Component Architecture
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@ -16,22 +17,25 @@ All components implement the base `Component` trait defined in `src/component.rs
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### CPU Components (`cpu/`)
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#### Intel 4004 CPU
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- **File**: `intel_4004.rs`
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- **Features**:
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- Complete Intel 4004 instruction set implementation
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- 4-bit data processing
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- 12-bit address space
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- Two-phase clock operation (Φ1, Φ2)
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- 16 general-purpose registers (8 index, 8 main)
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- Stack-based subroutine calls
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- Complete Intel 4004 instruction set implementation
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- 4-bit data processing
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- 12-bit address space
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- Two-phase clock operation (Φ1, Φ2)
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- 16 general-purpose registers (8 index, 8 main)
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- Stack-based subroutine calls
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- **Status**: Fully implemented with comprehensive testing
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#### MOS 6502 CPU (Placeholder)
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- **File**: `mos_6502.rs`
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- **Features**: Placeholder for MOS Technology 6502 implementation
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- **Status**: Not yet implemented
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#### WDC 65C02 CPU (Placeholder)
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- **File**: `wdc_65c02.rs`
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- **Features**: Placeholder for Western Design Center 65C02 implementation
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- **Status**: Not yet implemented
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@ -39,67 +43,74 @@ All components implement the base `Component` trait defined in `src/component.rs
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### Memory Components (`memory/`)
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#### Intel 4001 ROM
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- **File**: `intel_4001.rs`
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- **Features**:
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- 256 bytes of mask-programmable ROM
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- 4-bit I/O ports for peripheral interface
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- Two-phase addressing (8-bit address in two 4-bit cycles)
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- 500ns typical access time
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- SYNC signal detection for instruction fetch
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- 256 bytes of mask-programmable ROM
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- 4-bit I/O ports for peripheral interface
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- Two-phase addressing (8-bit address in two 4-bit cycles)
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- 500ns typical access time
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- SYNC signal detection for instruction fetch
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- **Status**: Fully implemented with comprehensive testing
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#### Intel 4002 RAM
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- **File**: `intel_4002.rs`
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- **Features**:
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- 320 bits of read/write memory (80 × 4-bit characters)
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- 4-bit output port for status/display
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- Banked memory organization (4 banks × 20 characters)
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- Refresh circuitry for dynamic memory cells
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- Status character instructions for control
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- 320 bits of read/write memory (80 × 4-bit characters)
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- 4-bit output port for status/display
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- Banked memory organization (4 banks × 20 characters)
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- Refresh circuitry for dynamic memory cells
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- Status character instructions for control
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- **Status**: Implemented with known limitations
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#### Intel 4003 Shift Register
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- **File**: `intel_4003.rs`
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- **Features**:
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- 10-bit static shift register
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- Serial input/output capability
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- Parallel input from data bus
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- 200ns typical access time
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- Bidirectional shifting
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- 10-bit static shift register
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- Serial input/output capability
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- Parallel input from data bus
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- 200ns typical access time
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- Bidirectional shifting
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- **Status**: Basic implementation
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#### Generic Memory Components
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- **GenericRAM**: `generic_ram.rs` - Configurable RAM implementation
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- **GenericROM**: `generic_rom.rs` - Configurable ROM implementation
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### Common Functionality (`common/`)
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#### Intel 400x Series Common Code
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- **File**: `intel_400x.rs`
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- **Purpose**: Shared functionality for all Intel 400x series chips
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- **Features**:
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- Common timing constants and state machines
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- Clock edge detection and handling
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- Data bus operations and bit manipulation
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- Address latching and assembly logic
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- Control pin reading and management
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- Reset handling and initialization
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- Memory operation state machines
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- Common timing constants and state machines
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- Clock edge detection and handling
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- Data bus operations and bit manipulation
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- Address latching and assembly logic
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- Control pin reading and management
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- Reset handling and initialization
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- Memory operation state machines
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### Clock Components (`clock/`)
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#### Generic Clock Generator
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- **File**: `generic_clock.rs`
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- **Features**:
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- Configurable frequency and duty cycle
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- Multiple output waveforms
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- Synchronization capabilities
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- Test pattern generation
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- Configurable frequency and duty cycle
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- Multiple output waveforms
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- Synchronization capabilities
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- Test pattern generation
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- **Status**: Basic implementation
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## Component Interface
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### Required Methods
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All components must implement:
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```rust
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@ -113,6 +124,7 @@ fn is_running(&self) -> bool; // Execution status
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```
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### Optional Traits
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Components can implement additional traits for specialized functionality:
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- **RunnableComponent**: Automatic thread spawning
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@ -122,12 +134,14 @@ Components can implement additional traits for specialized functionality:
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## Pin Configuration
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### Standard Pin Types
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- **Data Pins**: `D0-D3` for 4-bit data/address bus
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- **Clock Pins**: `PHI1`, `PHI2` for two-phase clock
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- **Control Pins**: `SYNC`, `RESET`, `CM`, `CI` for system control
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- **I/O Pins**: `IO0-IO3` for peripheral interface
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### Pin Signal States
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- **High**: Logic level 1
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- **Low**: Logic level 0
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- **HighZ**: High impedance (tri-state, not driving)
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@ -135,6 +149,7 @@ Components can implement additional traits for specialized functionality:
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## Usage Examples
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### Creating and Using a Component
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```rust
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use rusty_emu::components::memory::intel_4001::Intel4001;
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@ -143,38 +158,42 @@ let mut rom = Intel4001::new("ROM1".to_string());
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// Load program data
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let program = vec![0x12, 0x34, 0x56, 0x78];
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rom.load_rom_data(program, 0)?;
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rom.load_rom_data(program, 0) ?;
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// Use in simulation loop
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while simulation_running() {
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rom.update(); // Process one clock cycle
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rom.update(); // Process one clock cycle
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}
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```
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### Component Interconnection
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```rust
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// Components connect through shared pin references
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let cpu_pin = cpu.get_pin("D0")?;
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let rom_pin = rom.get_pin("D0")?;
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let ram_pin = ram.get_pin("D0")?;
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let cpu_pin = cpu.get_pin("D0") ?;
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let rom_pin = rom.get_pin("D0") ?;
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let ram_pin = ram.get_pin("D0") ?;
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// Connect pins together
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connect_pins(vec![cpu_pin, rom_pin, ram_pin])?;
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connect_pins(vec![cpu_pin, rom_pin, ram_pin]) ?;
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```
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## Testing Strategy
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### Unit Tests
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- Located in each component's implementation file
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- Test individual component behavior in isolation
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- Focus on state management and pin operations
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### Integration Tests
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- Located in `tests/` directory
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- Test component interactions and system behavior
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- Verify proper timing and signal propagation
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### Mock-Based Tests
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- Use mock components for controlled testing
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- Test error conditions and edge cases
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- Verify behavior with various input patterns
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@ -182,6 +201,7 @@ connect_pins(vec![cpu_pin, rom_pin, ram_pin])?;
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## Development Guidelines
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### Adding New Components
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1. **Implement Core Traits**: Start with `Component` trait implementation
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2. **Define Pin Configuration**: Specify required pins and their purposes
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3. **Implement Timing**: Add clock cycle processing in `update()` method
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6. **Update Exports**: Add the component to the appropriate module exports
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### Component Design Principles
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- **Single Responsibility**: Each component should have one primary function
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- **Clear Interfaces**: Well-defined pin configurations and behaviors
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- **Timing Awareness**: Proper handling of clock cycles and timing constraints
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- **Testability**: Design for easy testing and verification
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### Performance Considerations
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- **Pin Access**: Minimize lock contention on shared pins
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- **State Updates**: Efficient state machine transitions
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- **Memory Layout**: Optimize memory access patterns
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@ -205,6 +227,7 @@ connect_pins(vec![cpu_pin, rom_pin, ram_pin])?;
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## Hardware Accuracy
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### Intel 4004 Series Specifics
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- **Two-Phase Clock**: All operations synchronized to Φ1 and Φ2
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- **4-Bit Architecture**: Data processed in 4-bit nibbles
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- **12-Bit Addressing**: 8-bit addresses transferred in two 4-bit cycles
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- **Bus Sharing**: Multiple components share the same data bus
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### Implementation Notes
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- Some timing specifications are approximated due to Rust's timing limitations
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- Pin signal propagation is simplified for simulation performance
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- Bus contention handling prioritizes correctness over perfect hardware accuracy
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## Future Enhancements
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### Planned Components
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- Enhanced Intel 4002 RAM with proper refresh cycles
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- Intel 4008/4009 I/O expanders
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- Intel 4269 programmable ROM
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@ -227,6 +252,7 @@ connect_pins(vec![cpu_pin, rom_pin, ram_pin])?;
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- Cycle-accurate instruction execution
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### Architecture Improvements
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- Better pin signal propagation modeling
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- More sophisticated bus arbitration
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- Enhanced timing constraint checking
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