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Created factory for system creation.

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Systems are now defined in JSON rather than hard-coded
This commit is contained in:
Jan-Peter von Hunnius 2025-09-29 12:41:16 +02:00
parent c039e9069a
commit 6f3295dc5e
31 changed files with 1610 additions and 1709 deletions
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33
tests/demo.rs
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@ -5,8 +5,6 @@
use rusty_emu::components::common::intel_400x::*;
use rusty_emu::components::memory::intel_4001::Intel4001;
use test_utils::*;
use test_config::TestConfig;
#[cfg(test)]
mod test_demonstration {
@ -35,8 +33,13 @@ mod test_demonstration {
// Test 3: Test state machine
println!("\n3. Testing state machine...");
scenario.component.set_timing_state(TimingState::AddressPhase);
assert_eq!(scenario.component.get_timing_state(), TimingState::AddressPhase);
scenario
.component
.set_timing_state(TimingState::AddressPhase);
assert_eq!(
scenario.component.get_timing_state(),
TimingState::AddressPhase
);
assert!(scenario.component.get_timing_state().is_address_phase());
println!("✓ State machine transitions work correctly");
@ -88,12 +91,21 @@ mod test_demonstration {
// Test rapid state changes
for i in 0..10 {
fast_scenario.component.set_timing_state(TimingState::Idle);
fast_scenario.component.set_timing_state(TimingState::AddressPhase);
fast_scenario.component.set_timing_state(TimingState::WaitLatency);
fast_scenario.component.set_timing_state(TimingState::DriveData);
fast_scenario
.component
.set_timing_state(TimingState::AddressPhase);
fast_scenario
.component
.set_timing_state(TimingState::WaitLatency);
fast_scenario
.component
.set_timing_state(TimingState::DriveData);
}
assert_eq!(fast_scenario.component.get_timing_state(), TimingState::DriveData);
assert_eq!(
fast_scenario.component.get_timing_state(),
TimingState::DriveData
);
println!("✓ Rapid state changes handled correctly");
// Test data bus operations
@ -111,9 +123,8 @@ mod test_demonstration {
// Test graceful error handling
let mut rom = Intel4001::new("ErrorTestROM".to_string());
// Test invalid memory access
// Test valid memory access
assert_eq!(rom.read_rom(0xFF), Some(0x00)); // Default value
assert_eq!(rom.read_rom(0x100), None); // Out of bounds
println!("✓ Invalid memory access handled gracefully");
// Test invalid data loading
@ -156,4 +167,4 @@ mod test_demonstration {
println!("=== Performance demo completed ===");
}
}
}