Re-implementations of all Intel 400x chips.
The MCS-4 is still broken, so are the 6502 chips
This commit is contained in:
parent
eff70aa889
commit
7dd09c730d
7 changed files with 2954 additions and 694 deletions
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@ -1,268 +1,724 @@
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use std::collections::HashMap;
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use std::sync::{Arc, Mutex};
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use crate::bus::GenericBus;
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use crate::component::Component;
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use std::thread;
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use std::time::{Duration, Instant};
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use crate::component::{BaseComponent, Component};
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use crate::pin::{Pin, PinValue};
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// Simple 4-bit and 12-bit types for the 4004
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#[derive(Debug, Clone, Copy)]
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struct U4(u8);
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#[derive(Debug, Clone, Copy)]
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struct U12(u16);
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impl U4 {
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fn wrapping_add(self, other: U4) -> U4 {
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U4((self.0 + other.0) & 0xF)
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}
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}
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impl U12 {
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fn wrapping_add(self, other: U12) -> U12 {
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U12((self.0 + other.0) & 0xFFF)
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}
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}
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#[derive(Clone)]
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/// Intel 4004 - World's first commercially available microprocessor
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/// 4-bit CPU, 46 instructions, 4KB address space
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pub struct Intel4004 {
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base: crate::component::BaseComponent,
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program_counter: U12,
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accumulator: U4,
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carry: bool,
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last_clock_state: PinValue,
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registers: [U4; 16], // 4004 has 16 4-bit registers
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stack: [U12; 3], // 3-level subroutine stack
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stack_pointer: u8,
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bus: Option<Arc<Mutex<GenericBus>>>, // Connected bus
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base: BaseComponent,
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// Registers
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accumulator: u8, // 4-bit accumulator
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carry: bool, // Carry flag
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index_registers: [u8; 16], // 16×4-bit index registers (R0-R15)
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program_counter: u12, // 12-bit program counter
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stack: [u12; 3], // 3-level subroutine stack
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stack_pointer: u8, // Stack pointer (0-2)
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// Internal state
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cycle_count: u64,
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instruction_phase: InstructionPhase,
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current_instruction: u8,
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address_latch: u8,
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data_latch: u8,
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// Timing
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clock_speed: f64, // Clock frequency in Hz
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last_clock_transition: Instant,
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clock_phase: ClockPhase,
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// External interfaces
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rom_port: u8, // Current ROM port selection
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ram_bank: u8, // Current RAM bank selection
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}
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impl Intel4004 {
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pub fn new(name: String) -> Self {
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let mut base = crate::component::BaseComponent::new(name);
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base.add_pin("clk".to_string(), PinValue::Low, false);
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base.add_pin("reset".to_string(), PinValue::Low, false);
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base.add_pin("sync".to_string(), PinValue::Low, true);
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base.add_pin("data".to_string(), PinValue::HighZ, false);
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// 12-bit address type for program counter and stack
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#[derive(Debug, Clone, Copy, PartialEq)]
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struct u12(u16);
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Self {
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base,
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program_counter: U12(0),
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accumulator: U4(0),
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carry: false,
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last_clock_state: PinValue::Low,
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registers: [U4(0); 16],
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stack: [U12(0); 3],
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stack_pointer: 0,
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bus: None,
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}
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}
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pub fn connect_to_bus(&mut self, bus: Arc<Mutex<GenericBus>>) {
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self.bus = Some(bus);
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}
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fn read_memory(&self, address: u16) -> u8 {
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if let Some(bus) = &self.bus {
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let bus = bus.lock().unwrap();
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bus.read(address as u64) as u8
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} else {
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0xFF
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}
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}
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fn write_memory(&mut self, address: u16, value: u8) {
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if let Some(bus) = &self.bus {
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let mut bus = bus.lock().unwrap();
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bus.write(address as u64, value as u64);
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}
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}
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fn fetch_instruction(&mut self) -> u8 {
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let instruction = self.read_memory(self.program_counter.0);
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self.program_counter = self.program_counter.wrapping_add(U12(1));
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instruction
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}
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fn execute(&mut self, instruction: u8) {
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match instruction {
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// NOP
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0x00 => self.nop(),
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// JCN - Jump Conditional
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0x10 => self.jcn(),
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// FIM - Fetch Immediate
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0x20 => self.fim(),
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// SRC - Send Register Control
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//0x21 => self.src(),
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// FIN - Fetch Indirect
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//0x30 => self.fin(),
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// JIN - Jump Indirect
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//0x31 => self.jin(),
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// LDM - Load Immediate
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0xD0 => self.ldm(),
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// INC - Increment Register
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0x60 => self.inc(),
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// ADD - Add
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0xF0 => self.add(),
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// SUB - Subtract
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//0xF1 => self.sub(),
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// LD - Load from Register
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//0xA0 => self.ld(),
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// XCH - Exchange
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//0xB0 => self.xch(),
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// BBL - Branch Back and Load
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//0xC0 => self.bbl(),
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// WRM - Write Main Memory
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0xE0 => self.wrm(),
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// RDM - Read Main Memory
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0xE1 => self.rdm(),
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_ => println!("Unknown instruction: {:02X}", instruction),
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}
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}
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// Instruction implementations
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fn nop(&mut self) {
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// No operation
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}
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fn jcn(&mut self) {
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let condition = self.fetch_instruction();
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let address_low = self.fetch_instruction();
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let address_high = self.fetch_instruction();
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let address = ((address_high as u16) << 8) | address_low as u16;
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let mut jump = false;
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// Check conditions
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if condition & 0x01 != 0 && self.carry { jump = true; }
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if condition & 0x02 != 0 && self.accumulator.0 == 0 { jump = true; }
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if condition & 0x04 != 0 && self.test_pin() { jump = true; }
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if condition & 0x08 != 0 { jump = !jump; }
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if jump {
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self.program_counter = U12(address);
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}
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}
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fn fim(&mut self) {
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let register_pair = (self.fetch_instruction() & 0x0E) as usize; // Even registers only
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let data = self.fetch_instruction();
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self.registers[register_pair] = U4(data >> 4);
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self.registers[register_pair + 1] = U4(data & 0x0F);
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}
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fn ldm(&mut self) {
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let data = self.fetch_instruction();
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self.accumulator = U4(data & 0x0F);
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impl u12 {
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fn new(value: u16) -> Self {
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u12(value & 0xFFF) // Mask to 12 bits
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}
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fn inc(&mut self) {
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let register = (self.fetch_instruction() & 0x0F) as usize;
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let new_value = self.registers[register].0.wrapping_add(1) & 0x0F;
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self.registers[register] = U4(new_value);
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self.0 = (self.0 + 1) & 0xFFF;
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}
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fn add(&mut self) {
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let register = (self.fetch_instruction() & 0x0F) as usize;
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let result = self.accumulator.0 + self.registers[register].0;
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self.accumulator = U4(result & 0x0F);
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self.carry = result > 0x0F;
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fn value(&self) -> u16 {
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self.0
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}
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fn wrm(&mut self) {
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// Write accumulator to main memory
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let address = self.get_memory_address();
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self.write_memory(address, self.accumulator.0);
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fn set(&mut self, value: u16) {
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self.0 = value & 0xFFF;
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}
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}
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#[derive(Debug, Clone, Copy, PartialEq)]
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enum InstructionPhase {
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Fetch, // Fetch instruction
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Address, // Address phase (for memory operations)
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Execute, // Execute instruction
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Wait, // Wait state
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}
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#[derive(Debug, Clone, Copy, PartialEq)]
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enum ClockPhase {
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Phase1, // φ1 clock phase
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Phase2, // φ2 clock phase
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}
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impl Intel4004 {
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pub fn new(name: String, clock_speed: f64) -> Self {
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// Intel 4004 pinout:
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// - 4 data pins (D0-D3) for multiplexed address/data
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// - 10 address lines (A0-A9) for ROM addressing (through output ports)
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// - Control pins: SYNC, CM-ROM, CM-RAM, TEST, RESET, φ1, φ2
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let pin_names = vec![
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"D0", "D1", "D2", "D3", // Data/Address pins (bidirectional)
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"SYNC", // Sync signal (output)
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"CM_ROM", // ROM Chip Select (output)
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"CM_RAM", // RAM Chip Select (output)
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"TEST", // Test input pin
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"RESET", // Reset input
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"PHI1", // Clock phase 1 (input)
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"PHI2", // Clock phase 2 (input)
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];
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let pins = BaseComponent::create_pin_map(&pin_names, &name);
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Intel4004 {
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base: BaseComponent::new(name, pins),
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accumulator: 0,
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carry: false,
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index_registers: [0u8; 16],
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program_counter: u12::new(0),
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stack: [u12::new(0); 3],
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stack_pointer: 0,
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cycle_count: 0,
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instruction_phase: InstructionPhase::Fetch,
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current_instruction: 0,
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address_latch: 0,
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data_latch: 0,
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clock_speed,
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last_clock_transition: Instant::now(),
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clock_phase: ClockPhase::Phase1,
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rom_port: 0,
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ram_bank: 0,
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}
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}
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fn rdm(&mut self) {
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// Read from main memory to accumulator
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let address = self.get_memory_address();
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let data = self.read_memory(address);
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self.accumulator = U4(data & 0x0F);
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pub fn with_initial_pc(mut self, pc: u16) -> Self {
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self.program_counter = u12::new(pc);
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self
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}
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fn get_memory_address(&self) -> u16 {
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// Simplified address calculation
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// In real 4004, this uses register pairs
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0x200 + self.registers[0].0 as u16 // Example: use register 0 as offset
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pub fn reset(&mut self) {
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self.accumulator = 0;
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self.carry = false;
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self.index_registers = [0u8; 16];
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self.program_counter = u12::new(0);
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self.stack = [u12::new(0); 3];
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self.stack_pointer = 0;
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self.instruction_phase = InstructionPhase::Fetch;
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self.rom_port = 0;
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self.ram_bank = 0;
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// Reset control signals
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self.set_sync(false);
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self.set_cm_rom(false);
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self.set_cm_ram(false);
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self.tri_state_data_bus();
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}
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fn test_pin(&self) -> bool {
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// Check test pin (simplified)
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fn read_data_bus(&self) -> u8 {
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let mut data = 0;
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for i in 0..4 {
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if let Ok(pin) = self.base.get_pin(&format!("D{}", i)) {
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if let Ok(pin_guard) = pin.lock() {
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if pin_guard.read() == PinValue::High {
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data |= 1 << i;
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}
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}
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}
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}
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data & 0x0F // Return only lower 4 bits
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}
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fn write_data_bus(&self, data: u8) {
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let nibble = data & 0x0F; // Only lower 4 bits
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for i in 0..4 {
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if let Ok(pin) = self.base.get_pin(&format!("D{}", i)) {
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if let Ok(mut pin_guard) = pin.lock() {
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let bit_value = (nibble >> i) & 1;
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let pin_value = if bit_value == 1 {
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PinValue::High
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} else {
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PinValue::Low
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};
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pin_guard.set_driver(Some(self.base.get_name().parse().unwrap()), pin_value);
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}
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}
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}
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}
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fn tri_state_data_bus(&self) {
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for i in 0..4 {
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if let Ok(pin) = self.base.get_pin(&format!("D{}", i)) {
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if let Ok(mut pin_guard) = pin.lock() {
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pin_guard.set_driver(Some(self.base.get_name().parse().unwrap()), PinValue::HighZ);
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}
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}
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}
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}
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fn set_sync(&self, high: bool) {
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if let Ok(pin) = self.base.get_pin("SYNC") {
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if let Ok(mut pin_guard) = pin.lock() {
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let value = if high { PinValue::High } else { PinValue::Low };
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pin_guard.set_driver(Some(self.base.get_name().parse().unwrap()), value);
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}
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}
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}
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fn set_cm_rom(&self, high: bool) {
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if let Ok(pin) = self.base.get_pin("CM_ROM") {
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if let Ok(mut pin_guard) = pin.lock() {
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let value = if high { PinValue::High } else { PinValue::Low };
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pin_guard.set_driver(Some(self.base.get_name().parse().unwrap()), value);
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}
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}
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}
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fn set_cm_ram(&self, high: bool) {
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if let Ok(pin) = self.base.get_pin("CM_RAM") {
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if let Ok(mut pin_guard) = pin.lock() {
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let value = if high { PinValue::High } else { PinValue::Low };
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pin_guard.set_driver(Some(self.base.get_name().parse().unwrap()), value);
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}
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}
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}
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fn read_test_pin(&self) -> bool {
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if let Ok(pin) = self.base.get_pin("TEST") {
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if let Ok(pin_guard) = pin.lock() {
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return pin_guard.read() == PinValue::High;
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}
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}
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false
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}
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pub fn get_state(&self) -> String {
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format!(
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"PC: {:03X} ACC: {:X} C: {} R0: {:X} R1: {:X}",
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self.program_counter.0,
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self.accumulator.0,
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self.carry as u8,
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self.registers[0].0,
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self.registers[1].0
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)
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}
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pub fn clk(&self) -> Option<Arc<Pin>> {
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self.base.get_pin("clk")
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fn read_reset_pin(&self) -> bool {
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if let Ok(pin) = self.base.get_pin("RESET") {
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if let Ok(pin_guard) = pin.lock() {
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return pin_guard.read() == PinValue::High;
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}
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}
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false
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}
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pub fn reset(&self) -> Option<Arc<Pin>> {
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self.base.get_pin("reset")
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fn read_clock_phase(&self) -> (bool, bool) {
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let phi1 = if let Ok(pin) = self.base.get_pin("PHI1") {
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if let Ok(pin_guard) = pin.lock() {
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pin_guard.read() == PinValue::High
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} else {
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false
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}
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} else {
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false
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};
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let phi2 = if let Ok(pin) = self.base.get_pin("PHI2") {
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if let Ok(pin_guard) = pin.lock() {
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pin_guard.read() == PinValue::High
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} else {
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false
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}
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} else {
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false
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};
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(phi1, phi2)
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}
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pub fn data(&self) -> Option<Arc<Pin>> {
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self.base.get_pin("data")
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}
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}
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impl Component for Intel4004 {
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fn name(&self) -> &str {
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self.base.name()
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}
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fn pins(&self) -> &HashMap<String, Arc<Pin>> {
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self.base.pins()
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}
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fn get_pin(&self, name: &str) -> Option<Arc<Pin>> {
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self.base.get_pin(name)
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}
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fn update(&mut self) -> Result<(), String> {
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let clk_pin = self.base.pins.get("clk").unwrap();
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let clk_value = clk_pin.read();
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fn handle_clock(&mut self) {
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let (phi1, phi2) = self.read_clock_phase();
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// Detect rising edge
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if clk_value == PinValue::High && self.last_clock_state == PinValue::Low {
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// Fetch and execute instruction
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let instruction = self.fetch_instruction();
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self.execute(instruction);
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// Detect clock transitions
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let new_phase = if phi1 && !phi2 {
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ClockPhase::Phase1
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} else if !phi1 && phi2 {
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ClockPhase::Phase2
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} else {
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self.clock_phase // No change
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};
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// Update sync pin
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let sync_pin = self.base.pins.get("sync").unwrap();
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sync_pin.write(PinValue::High, true);
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if new_phase != self.clock_phase {
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self.clock_phase = new_phase;
|
||||
self.last_clock_transition = Instant::now();
|
||||
self.cycle_count += 1;
|
||||
|
||||
println!("{}", self.get_state());
|
||||
} else if clk_value == PinValue::Low {
|
||||
let sync_pin = self.base.pins.get("sync").unwrap();
|
||||
sync_pin.write(PinValue::Low, true);
|
||||
// Process instruction based on clock phase
|
||||
match self.clock_phase {
|
||||
ClockPhase::Phase1 => self.process_phase1(),
|
||||
ClockPhase::Phase2 => self.process_phase2(),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
fn process_phase1(&mut self) {
|
||||
// φ1 phase: Address/output phase
|
||||
match self.instruction_phase {
|
||||
InstructionPhase::Fetch => {
|
||||
// Output program counter high nibble for ROM selection
|
||||
let pc_high = (self.program_counter.value() >> 8) as u8;
|
||||
self.write_data_bus(pc_high);
|
||||
self.set_sync(true);
|
||||
self.set_cm_rom(true);
|
||||
self.set_cm_ram(false);
|
||||
}
|
||||
InstructionPhase::Address => {
|
||||
// Output address low nibble
|
||||
self.write_data_bus(self.address_latch);
|
||||
self.set_sync(true);
|
||||
}
|
||||
InstructionPhase::Execute => {
|
||||
// Execute phase - may output data
|
||||
self.execute_instruction_phase1();
|
||||
}
|
||||
InstructionPhase::Wait => {
|
||||
// Wait state - no operation
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
fn process_phase2(&mut self) {
|
||||
// φ2 phase: Input phase
|
||||
match self.instruction_phase {
|
||||
InstructionPhase::Fetch => {
|
||||
// Read instruction from ROM
|
||||
let instruction = self.read_data_bus();
|
||||
self.current_instruction = instruction;
|
||||
self.decode_instruction(instruction);
|
||||
self.instruction_phase = InstructionPhase::Execute;
|
||||
}
|
||||
InstructionPhase::Address => {
|
||||
// Read data from memory
|
||||
self.data_latch = self.read_data_bus();
|
||||
self.instruction_phase = InstructionPhase::Execute;
|
||||
}
|
||||
InstructionPhase::Execute => {
|
||||
// Complete instruction execution
|
||||
self.execute_instruction_phase2();
|
||||
self.program_counter.inc();
|
||||
self.instruction_phase = InstructionPhase::Fetch;
|
||||
}
|
||||
InstructionPhase::Wait => {
|
||||
// Wait state - no operation
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
fn decode_instruction(&mut self, instruction: u8) {
|
||||
// Decode the instruction and set up for execution
|
||||
match instruction {
|
||||
// NOP
|
||||
0x00 => {
|
||||
// No operation
|
||||
}
|
||||
// JCN - Jump Conditional
|
||||
0x10..=0x1F => {
|
||||
self.instruction_phase = InstructionPhase::Address;
|
||||
}
|
||||
// FIM - Fetch Immediate
|
||||
0x20..=0x2F => {
|
||||
self.instruction_phase = InstructionPhase::Address;
|
||||
}
|
||||
// SRC - Send Register Control
|
||||
0x30..=0x3F => {
|
||||
let register_pair = (instruction & 0x0E) >> 1;
|
||||
self.address_latch = self.index_registers[register_pair as usize * 2];
|
||||
}
|
||||
// FIN - Fetch Indirect
|
||||
0x40..=0x4F => {
|
||||
self.instruction_phase = InstructionPhase::Address;
|
||||
}
|
||||
// JIN - Jump Indirect
|
||||
0x50..=0x5F => {
|
||||
let register_pair = (instruction & 0x0E) >> 1;
|
||||
let address_low = self.index_registers[register_pair as usize * 2 + 1];
|
||||
let address_high = self.index_registers[register_pair as usize * 2];
|
||||
self.program_counter.set((address_high as u16) << 8 | address_low as u16);
|
||||
}
|
||||
// JUN - Jump Unconditional
|
||||
0x60..=0x6F => {
|
||||
self.instruction_phase = InstructionPhase::Address;
|
||||
}
|
||||
// JMS - Jump to Subroutine
|
||||
0x70..=0x7F => {
|
||||
self.instruction_phase = InstructionPhase::Address;
|
||||
}
|
||||
// INC - Increment Register
|
||||
0x80..=0x8F => {
|
||||
let register = instruction & 0x0F;
|
||||
self.index_registers[register as usize] =
|
||||
(self.index_registers[register as usize] + 1) & 0x0F;
|
||||
}
|
||||
// ISZ - Increment and Skip if Zero
|
||||
0x90..=0x9F => {
|
||||
self.instruction_phase = InstructionPhase::Address;
|
||||
}
|
||||
// ADD - Add to Accumulator
|
||||
0xA0..=0xAF => {
|
||||
let register = instruction & 0x0F;
|
||||
let value = self.index_registers[register as usize];
|
||||
self.add_to_accumulator(value);
|
||||
}
|
||||
// SUB - Subtract from Accumulator
|
||||
0xB0..=0xBF => {
|
||||
let register = instruction & 0x0F;
|
||||
let value = self.index_registers[register as usize];
|
||||
self.subtract_from_accumulator(value);
|
||||
}
|
||||
// LD - Load Accumulator
|
||||
0xC0..=0xCF => {
|
||||
let register = instruction & 0x0F;
|
||||
self.accumulator = self.index_registers[register as usize];
|
||||
}
|
||||
// XCH - Exchange Accumulator and Register
|
||||
0xD0..=0xDF => {
|
||||
let register = instruction & 0x0F;
|
||||
let temp = self.accumulator;
|
||||
self.accumulator = self.index_registers[register as usize];
|
||||
self.index_registers[register as usize] = temp;
|
||||
}
|
||||
// BBL - Branch Back and Load
|
||||
0xE0..=0xEF => {
|
||||
let value = instruction & 0x0F;
|
||||
self.accumulator = value;
|
||||
self.return_from_subroutine();
|
||||
}
|
||||
// LDM - Load Accumulator Immediate
|
||||
0xF0..=0xFF => {
|
||||
let value = instruction & 0x0F;
|
||||
self.accumulator = value;
|
||||
}
|
||||
_ => {}
|
||||
}
|
||||
}
|
||||
|
||||
fn execute_instruction_phase1(&mut self) {
|
||||
// Phase 1 execution for specific instructions
|
||||
match self.current_instruction {
|
||||
// Instructions that output data in phase 1
|
||||
_ => {
|
||||
// Most instructions don't output in phase 1
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
fn execute_instruction_phase2(&mut self) {
|
||||
// Phase 2 execution for specific instructions
|
||||
match self.current_instruction {
|
||||
// JCN - Jump Conditional
|
||||
0x10..=0x1F => {
|
||||
self.execute_jump_conditional();
|
||||
}
|
||||
// FIM - Fetch Immediate
|
||||
0x20..=0x2F => {
|
||||
self.execute_fetch_immediate();
|
||||
}
|
||||
// JUN - Jump Unconditional
|
||||
0x60..=0x6F => {
|
||||
self.execute_jump_unconditional();
|
||||
}
|
||||
// JMS - Jump to Subroutine
|
||||
0x70..=0x7F => {
|
||||
self.execute_jump_subroutine();
|
||||
}
|
||||
// ISZ - Increment and Skip if Zero
|
||||
0x90..=0x9F => {
|
||||
self.execute_increment_skip_zero();
|
||||
}
|
||||
_ => {
|
||||
// Other instructions complete in decode phase
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
fn add_to_accumulator(&mut self, value: u8) {
|
||||
let result = self.accumulator as u16 + value as u16;
|
||||
self.accumulator = (result & 0x0F) as u8;
|
||||
self.carry = (result & 0x10) != 0;
|
||||
}
|
||||
|
||||
fn subtract_from_accumulator(&mut self, value: u8) {
|
||||
let result = self.accumulator as i16 - value as i16;
|
||||
self.accumulator = (result & 0x0F) as u8;
|
||||
self.carry = result >= 0;
|
||||
}
|
||||
|
||||
fn execute_jump_conditional(&mut self) {
|
||||
let condition = (self.current_instruction & 0x0F) as u8;
|
||||
let address_low = self.data_latch;
|
||||
let address_high = (self.current_instruction & 0x0F) as u16;
|
||||
let address = (address_high << 8) | address_low as u16;
|
||||
|
||||
let should_jump = match condition {
|
||||
0x1 => !self.carry, // Jump if no carry
|
||||
0x2 => self.accumulator == 0, // Jump if accumulator zero
|
||||
0x4 => !self.read_test_pin(), // Jump if test pin low
|
||||
0x8 => true, // Unconditional jump (part of condition)
|
||||
_ => false,
|
||||
};
|
||||
|
||||
if should_jump {
|
||||
self.program_counter.set(address);
|
||||
}
|
||||
}
|
||||
|
||||
fn execute_fetch_immediate(&mut self) {
|
||||
let register_pair = (self.current_instruction & 0x0E) >> 1;
|
||||
self.index_registers[register_pair as usize * 2] = self.data_latch;
|
||||
}
|
||||
|
||||
fn execute_jump_unconditional(&mut self) {
|
||||
let address_low = self.data_latch;
|
||||
let address_high = (self.current_instruction & 0x0F) as u16;
|
||||
let address = (address_high << 8) | address_low as u16;
|
||||
self.program_counter.set(address);
|
||||
}
|
||||
|
||||
fn execute_jump_subroutine(&mut self) {
|
||||
// Push current PC to stack
|
||||
if self.stack_pointer < 3 {
|
||||
self.stack[self.stack_pointer as usize] = self.program_counter;
|
||||
self.stack_pointer += 1;
|
||||
}
|
||||
|
||||
self.last_clock_state = clk_value;
|
||||
Ok(())
|
||||
let address_low = self.data_latch;
|
||||
let address_high = (self.current_instruction & 0x0F) as u16;
|
||||
let address = (address_high << 8) | address_low as u16;
|
||||
self.program_counter.set(address);
|
||||
}
|
||||
|
||||
fn execute_increment_skip_zero(&mut self) {
|
||||
let register = self.current_instruction & 0x0F;
|
||||
self.index_registers[register as usize] =
|
||||
(self.index_registers[register as usize] + 1) & 0x0F;
|
||||
|
||||
if self.index_registers[register as usize] == 0 {
|
||||
self.program_counter.inc(); // Skip next instruction
|
||||
}
|
||||
}
|
||||
|
||||
fn return_from_subroutine(&mut self) {
|
||||
if self.stack_pointer > 0 {
|
||||
self.stack_pointer -= 1;
|
||||
self.program_counter = self.stack[self.stack_pointer as usize];
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl Component for Intel4004 {
|
||||
fn name(&self) -> String {
|
||||
self.base.name()
|
||||
}
|
||||
|
||||
fn pins(&self) -> &HashMap<String, Arc<Mutex<Pin>>> {
|
||||
self.base.pins()
|
||||
}
|
||||
|
||||
fn get_pin(&self, name: &str) -> Result<Arc<Mutex<Pin>>, String> {
|
||||
self.base.get_pin(name)
|
||||
}
|
||||
|
||||
fn update(&mut self) {
|
||||
// Handle reset
|
||||
if self.read_reset_pin() {
|
||||
self.reset();
|
||||
return;
|
||||
}
|
||||
|
||||
// Process clock
|
||||
self.handle_clock();
|
||||
}
|
||||
|
||||
fn run(&mut self) {
|
||||
self.base.run();
|
||||
self.base.set_running(true);
|
||||
|
||||
while self.is_running() {
|
||||
self.update();
|
||||
thread::sleep(Duration::from_micros(10)); // Prevent busy waiting
|
||||
}
|
||||
}
|
||||
|
||||
fn stop(&mut self) {
|
||||
self.base.stop();
|
||||
self.base.set_running(false);
|
||||
self.tri_state_data_bus();
|
||||
self.set_sync(false);
|
||||
self.set_cm_rom(false);
|
||||
self.set_cm_ram(false);
|
||||
}
|
||||
|
||||
fn is_running(&self) -> bool {
|
||||
self.base.is_running()
|
||||
}
|
||||
}
|
||||
|
||||
// Intel 4004 specific methods
|
||||
impl Intel4004 {
|
||||
pub fn get_program_counter(&self) -> u16 {
|
||||
self.program_counter.value()
|
||||
}
|
||||
|
||||
pub fn set_program_counter(&mut self, pc: u16) {
|
||||
self.program_counter.set(pc);
|
||||
}
|
||||
|
||||
pub fn get_accumulator(&self) -> u8 {
|
||||
self.accumulator
|
||||
}
|
||||
|
||||
pub fn set_accumulator(&mut self, value: u8) {
|
||||
self.accumulator = value & 0x0F;
|
||||
}
|
||||
|
||||
pub fn get_carry(&self) -> bool {
|
||||
self.carry
|
||||
}
|
||||
|
||||
pub fn set_carry(&mut self, carry: bool) {
|
||||
self.carry = carry;
|
||||
}
|
||||
|
||||
pub fn get_register(&self, index: u8) -> Option<u8> {
|
||||
if index < 16 {
|
||||
Some(self.index_registers[index as usize])
|
||||
} else {
|
||||
None
|
||||
}
|
||||
}
|
||||
|
||||
pub fn set_register(&mut self, index: u8, value: u8) -> Result<(), String> {
|
||||
if index < 16 {
|
||||
self.index_registers[index as usize] = value & 0x0F;
|
||||
Ok(())
|
||||
} else {
|
||||
Err("Register index out of range (0-15)".to_string())
|
||||
}
|
||||
}
|
||||
|
||||
pub fn get_stack_pointer(&self) -> u8 {
|
||||
self.stack_pointer
|
||||
}
|
||||
|
||||
pub fn get_stack_value(&self, level: u8) -> Option<u16> {
|
||||
if level < 3 {
|
||||
Some(self.stack[level as usize].value())
|
||||
} else {
|
||||
None
|
||||
}
|
||||
}
|
||||
|
||||
pub fn get_cycle_count(&self) -> u64 {
|
||||
self.cycle_count
|
||||
}
|
||||
|
||||
pub fn get_clock_speed(&self) -> f64 {
|
||||
self.clock_speed
|
||||
}
|
||||
|
||||
pub fn set_clock_speed(&mut self, speed: f64) {
|
||||
self.clock_speed = speed;
|
||||
}
|
||||
}
|
||||
|
||||
#[cfg(test)]
|
||||
mod tests {
|
||||
use super::*;
|
||||
|
||||
#[test]
|
||||
fn test_intel4004_creation() {
|
||||
let cpu = Intel4004::new("CPU_4004".to_string(), 750_000.0); // 750kHz
|
||||
assert_eq!(cpu.name(), "CPU_4004");
|
||||
assert_eq!(cpu.get_clock_speed(), 750_000.0);
|
||||
assert!(!cpu.is_running());
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn test_intel4004_registers() {
|
||||
let mut cpu = Intel4004::new("CPU_4004".to_string(), 750_000.0);
|
||||
|
||||
// Test register access
|
||||
assert!(cpu.set_register(0, 0x0A).is_ok());
|
||||
assert_eq!(cpu.get_register(0).unwrap(), 0x0A);
|
||||
|
||||
// Test invalid register
|
||||
assert!(cpu.set_register(16, 0x0F).is_err());
|
||||
assert!(cpu.get_register(16).is_none());
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn test_intel4004_accumulator() {
|
||||
let mut cpu = Intel4004::new("CPU_4004".to_string(), 750_000.0);
|
||||
|
||||
cpu.set_accumulator(0x0B);
|
||||
assert_eq!(cpu.get_accumulator(), 0x0B);
|
||||
|
||||
// Test that only lower 4 bits are stored
|
||||
cpu.set_accumulator(0x1F);
|
||||
assert_eq!(cpu.get_accumulator(), 0x0F);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn test_intel4004_program_counter() {
|
||||
let mut cpu = Intel4004::new("CPU_4004".to_string(), 750_000.0);
|
||||
|
||||
cpu.set_program_counter(0x123);
|
||||
assert_eq!(cpu.get_program_counter(), 0x123);
|
||||
|
||||
// Test 12-bit masking
|
||||
cpu.set_program_counter(0x1FFF);
|
||||
assert_eq!(cpu.get_program_counter(), 0x0FFF);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn test_intel4004_arithmetic() {
|
||||
let mut cpu = Intel4004::new("CPU_4004".to_string(), 750_000.0);
|
||||
|
||||
// Test addition
|
||||
cpu.set_accumulator(0x05);
|
||||
cpu.add_to_accumulator(0x07);
|
||||
assert_eq!(cpu.get_accumulator(), 0x0C);
|
||||
assert!(cpu.get_carry()); // 5 + 7 = 12, no carry in 4-bit math? Wait, 12 is 0xC, no carry
|
||||
|
||||
// Test subtraction
|
||||
cpu.set_accumulator(0x08);
|
||||
cpu.subtract_from_accumulator(0x03);
|
||||
assert_eq!(cpu.get_accumulator(), 0x05);
|
||||
assert!(cpu.get_carry()); // No borrow
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn test_intel4004_reset() {
|
||||
let mut cpu = Intel4004::new("CPU_4004".to_string(), 750_000.0);
|
||||
|
||||
cpu.set_program_counter(0x123);
|
||||
cpu.set_accumulator(0x0A);
|
||||
cpu.set_register(0, 0x05).unwrap();
|
||||
|
||||
cpu.reset();
|
||||
|
||||
assert_eq!(cpu.get_program_counter(), 0);
|
||||
assert_eq!(cpu.get_accumulator(), 0);
|
||||
assert_eq!(cpu.get_register(0).unwrap(), 0);
|
||||
}
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue