Re-implementations of all Intel 400x chips.
The MCS-4 is still broken, so are the 6502 chips
This commit is contained in:
parent
eff70aa889
commit
7dd09c730d
7 changed files with 2954 additions and 694 deletions
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@ -1,105 +1,452 @@
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use std::collections::HashMap;
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use std::sync::{Arc, Mutex};
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use std::thread;
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use std::time::Duration;
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use crate::component::Component;
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use crate::components::clock::generic_clock::GenericClock;
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use crate::components::cpu::intel_4004::Intel4004;
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use crate::components::memory::intel_4001::Intel4001;
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use crate::components::memory::intel_4002::Intel4002;
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use crate::{connect_pins, Component, PinValue};
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use crate::bus::GenericBus;
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#[derive(Clone, Copy, PartialEq)]
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pub enum MCS4Phase {
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AddressLow, // Send address low nibble
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AddressHigh, // Send address high nibble + middle
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Instruction, // Fetch instruction
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DataRead, // Read data
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DataWrite, // Write data
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}
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pub fn run_fibonacci_calculator() {
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println!("Starting MCS-4 Fibonacci Calculator...");
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use crate::connection::ConnectionManager;
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use crate::pin::Pin;
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// Create components
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let mut clock = GenericClock::new("CLK".parse().unwrap(), 1000);
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let mut bus = GenericBus::new("BUS_MCS-4".parse().unwrap(), &[("B0", PinValue::HighZ),("B1", PinValue::HighZ),("B2", PinValue::HighZ),("B3", PinValue::HighZ)]);
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let cpu = Arc::new(Mutex::new(Intel4004::new("cpu4004".to_string())));
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// ROM 0: responds to addresses with high nibble 0x0
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let rom0 = Arc::new(Mutex::new(Intel4001::new("rom0".to_string(), 0x0)));
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// ROM 1: responds to addresses with high nibble 0x1
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let rom1 = Arc::new(Mutex::new(Intel4001::new("rom1".to_string(), 0x1)));
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// RAM bank 0: responds to addresses 0x400-0x47F
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let ram0 = Arc::new(Mutex::new(Intel4002::new("ram0".to_string(), 0x400, 3, 2)));
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// Connect all devices to the bus
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bus.connect_device(cpu.clone());
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bus.connect_device(rom0.clone());
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bus.connect_device(rom1.clone());
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bus.connect_device(ram0.clone());
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// Connect clock to CPU
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if let (Some(clock_out), Some(cpu_clk)) = (clock.out(), cpu.clk()) {
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connect_pins(&clock_out, &cpu_clk).expect("Clock connection failed");
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println!("Connected clock to CPU");
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}
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// Start components
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clock.run();
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cpu.run();
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load_fibonacci_program(rom0.clone());
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// Let it run for a while
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thread::sleep(Duration::from_secs(10));
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// Read results from RAM
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let bus_lock = bus.lock().unwrap();
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let result1 = bus_lock.read(0x0200); // Fibonacci numbers stored here
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let result2 = bus_lock.read(0x0201);
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println!("Fibonacci results: {}, {}", result1, result2);
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// Stop components
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clock.stop();
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cpu.stop();
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println!("Fibonacci calculation completed");
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/// Complete Intel MCS-4 Microcomputer System
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/// Contains: 4004 CPU, clock, 4002 RAM, and two 4001 ROM chips
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pub struct IntelMcs4 {
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components: HashMap<String, Box<dyn Component>>,
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connection_manager: ConnectionManager,
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is_running: bool,
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}
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fn load_fibonacci_program(rom: Arc<Mutex<Intel4001>>) {
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let mut rom_lock = rom.lock().unwrap();
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impl IntelMcs4 {
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pub fn new() -> Self {
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let mut system = IntelMcs4 {
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components: HashMap::new(),
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connection_manager: ConnectionManager::new(),
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is_running: false,
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};
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// Simple Fibonacci program in 4004 machine code
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let program = vec![
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0x20, 0x00, // FIM R0,R1 = 0,0 (initialize)
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0x20, 0x11, // FIM R2,R3 = 1,1 (Fibonacci seed)
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0x20, 0x00, // FIM R4,R5 = 0,0 (counter)
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// Main loop
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0xA0, // LD R0 (load first number)
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0xA2, // LD R2 (load second number)
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0xF0, // ADD R0 (R0 + R2)
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0xE0, // WRM (store result)
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0xB0, // XCH R2 (move R2 to R0)
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0xA0, // LD R0 (get result)
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0xB2, // XCH R2 (update second number)
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// Increment counter
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0x64, // INC R4
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0x10, 0x01, 0x00, // JCN (loop condition)
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// Store results
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0xA0, 0xE0, // LD R0, WRM (store final result 1)
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0xA2, 0xE1, // LD R2, WRM (store final result 2)
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0x00, // NOP
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];
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// Load program into ROM
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let mut rom_data = Vec::new();
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for &byte in &program {
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rom_data.push(byte as u64);
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system.initialize_system();
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system
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}
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rom_lock.load_data(&rom_data);
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println!("Loaded Fibonacci program into ROM");
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fn initialize_system(&mut self) {
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// Create components with historically accurate configuration
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// 4004 CPU - 750kHz clock speed (original MCS-4 speed)
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let cpu = Intel4004::new("CPU_4004".to_string(), 750_000.0)
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.with_initial_pc(0x000);
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// System clock - 750kHz, 50% duty cycle
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let clock = GenericClock::new("SYSTEM_CLOCK".to_string(), 750_000.0)
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.with_duty_cycle(0.5);
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// 4002 RAM - 320 bits (40 nibbles)
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let ram = Intel4002::new("RAM_4002".to_string());
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// Two 4001 ROM chips (256 bytes each = 512 bytes total ROM)
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let rom1 = Intel4001::new("ROM_4001_1".to_string());
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let rom2 = Intel4001::new("ROM_4001_2".to_string());
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// Store components
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self.components.insert("cpu".to_string(), Box::new(cpu));
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self.components.insert("clock".to_string(), Box::new(clock));
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self.components.insert("ram".to_string(), Box::new(ram));
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self.components.insert("rom1".to_string(), Box::new(rom1));
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self.components.insert("rom2".to_string(), Box::new(rom2));
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// Connect the system
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self.connect_system();
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}
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fn connect_system(&mut self) {
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// Get references to all components' pins
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let cpu = self.components.get("cpu").unwrap();
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let clock = self.components.get("clock").unwrap();
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let ram = self.components.get("ram").unwrap();
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let rom1 = self.components.get("rom1").unwrap();
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let rom2 = self.components.get("rom2").unwrap();
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// Connect clock to CPU
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if let (Ok(cpu_phi1), Ok(cpu_phi2), Ok(clk_out)) = (
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cpu.get_pin("PHI1"),
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cpu.get_pin("PHI2"),
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clock.get_pin("CLK")
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) {
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// Clock drives both CPU phase inputs (inverted for phase 2)
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let _ = self.connection_manager.connect_pins(clk_out.clone(), cpu_phi1.clone());
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// Note: In real system, φ2 would be inverted φ1
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}
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// Connect data bus (D0-D3) between all components
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for i in 0..4 {
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let data_pin_name = format!("D{}", i);
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if let (Ok(cpu_data), Ok(ram_data), Ok(rom1_data), Ok(rom2_data)) = (
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cpu.get_pin(&data_pin_name),
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ram.get_pin(&data_pin_name),
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rom1.get_pin(&data_pin_name),
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rom2.get_pin(&data_pin_name),
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) {
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// Connect all data pins together (bus)
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let bus_pins = vec![cpu_data.clone(), ram_data.clone(), rom1_data.clone(), rom2_data.clone()];
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let _ = self.connection_manager.connect_bus(&bus_pins);
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}
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}
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// Connect control signals
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// SYNC signal (CPU → all chips)
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if let (Ok(cpu_sync), Ok(ram_sync), Ok(rom1_sync), Ok(rom2_sync)) = (
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cpu.get_pin("SYNC"),
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ram.get_pin("SYNC"),
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rom1.get_pin("SYNC"),
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rom2.get_pin("SYNC"),
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) {
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let sync_pins = vec![cpu_sync.clone(), ram_sync.clone(), rom1_sync.clone(), rom2_sync.clone()];
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let _ = self.connection_manager.connect_bus(&sync_pins);
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}
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// CM-ROM signal (CPU → ROM chips)
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if let (Ok(cpu_cm_rom), Ok(rom1_cm_rom), Ok(rom2_cm_rom)) = (
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cpu.get_pin("CM_ROM"),
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rom1.get_pin("CM_ROM"),
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rom2.get_pin("CM_ROM"),
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) {
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let cm_rom_pins = vec![cpu_cm_rom.clone(), rom1_cm_rom.clone(), rom2_cm_rom.clone()];
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let _ = self.connection_manager.connect_bus(&cm_rom_pins);
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}
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// CM-RAM signal (CPU → RAM chip)
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if let (Ok(cpu_cm_ram), Ok(ram_cm_ram)) = (
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cpu.get_pin("CM_RAM"),
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ram.get_pin("CM_RAM"),
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) {
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let _ = self.connection_manager.connect_pins(cpu_cm_ram.clone(), ram_cm_ram.clone());
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}
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// RESET signal (external → all chips)
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// Create a system reset pin
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let reset_pin = Arc::new(Mutex::new(Pin::new("SYSTEM_RESET".to_string())));
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if let (Ok(cpu_reset), Ok(ram_reset), Ok(rom1_reset), Ok(rom2_reset)) = (
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cpu.get_pin("RESET"),
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ram.get_pin("RESET"),
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rom1.get_pin("RESET"),
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rom2.get_pin("RESET"),
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) {
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let reset_pins = vec![reset_pin.clone(), cpu_reset.clone(), ram_reset.clone(), rom1_reset.clone(), rom2_reset.clone()];
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let _ = self.connection_manager.connect_bus(&reset_pins);
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}
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// Connect ROM output ports to form higher address lines
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// In MCS-4, ROM output ports provide address lines A8-A11
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if let (Ok(rom1_io0), Ok(rom2_io0)) = (rom1.get_pin("IO0"), rom2.get_pin("IO0")) {
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// These would be connected to address decoding logic in a real system
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// For now, we'll connect them together as a simple bus
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let _ = self.connection_manager.connect_pins(rom1_io0.clone(), rom2_io0.clone());
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}
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// Note: In a real MCS-4 system, there would be more complex wiring
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// for bank selection and I/O expansion
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}
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pub fn load_rom_data(&mut self, rom_chip: usize, data: Vec<u8>, offset: usize) -> Result<(), String> {
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let rom_key = match rom_chip {
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1 => "rom1",
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2 => "rom2",
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_ => return Err("Invalid ROM chip number (1 or 2)".to_string()),
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};
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if let Some(rom_component) = self.components.get_mut(rom_key) {
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// Downcast to Intel4001 to call ROM-specific methods
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if let Some(rom) = rom_component.as_any_mut().downcast_mut::<Intel4001>() {
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rom.load_rom_data(data, offset)
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} else {
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Err("Component is not an Intel4001".to_string())
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}
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} else {
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Err(format!("ROM chip {} not found", rom_chip))
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}
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}
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pub fn load_ram_data(&mut self, data: &[u8], offset: usize) -> Result<(), String> {
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if let Some(ram_component) = self.components.get_mut("ram") {
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if let Some(ram) = ram_component.as_any_mut().downcast_mut::<Intel4002>() {
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ram.initialize_ram(data)
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} else {
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Err("Component is not an Intel4002".to_string())
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}
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} else {
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Err("RAM component not found".to_string())
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}
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}
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pub fn set_cpu_program_counter(&mut self, address: u16) -> Result<(), String> {
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if let Some(cpu_component) = self.components.get_mut("cpu") {
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if let Some(cpu) = cpu_component.as_any_mut().downcast_mut::<Intel4004>() {
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cpu.set_program_counter(address);
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Ok(())
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} else {
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Err("Component is not an Intel4004".to_string())
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}
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} else {
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Err("CPU component not found".to_string())
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}
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}
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pub fn get_cpu_state(&self) -> Result<CpuState, String> {
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if let Some(cpu_component) = self.components.get("cpu") {
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if let Some(cpu) = cpu_component.as_any().downcast_ref::<Intel4004>() {
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Ok(CpuState {
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program_counter: cpu.get_program_counter(),
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accumulator: cpu.get_accumulator(),
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carry: cpu.get_carry(),
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stack_pointer: cpu.get_stack_pointer(),
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cycle_count: cpu.get_cycle_count(),
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})
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} else {
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Err("Component is not an Intel4004".to_string())
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}
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} else {
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Err("CPU component not found".to_string())
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}
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}
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pub fn reset_system(&mut self) {
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// Reset all components
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for component in self.components.values_mut() {
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if let Some(cpu) = component.as_any_mut().downcast_mut::<Intel4004>() {
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cpu.reset();
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} else if let Some(ram) = component.as_any_mut().downcast_mut::<Intel4002>() {
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// RAM reset would clear registers but not memory
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} else if let Some(rom) = component.as_any_mut().downcast_mut::<Intel4001>() {
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// ROM reset would clear I/O latches
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}
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}
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// Pulse the system reset line
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if let Some(reset_pin) = self.connection_manager.get_pin("SYSTEM_RESET") {
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if let Ok(mut pin_guard) = reset_pin.lock() {
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// Pulse reset high then low
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pin_guard.set_driver(Some("system".to_string()), crate::pin::PinValue::High);
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// In a real implementation, we'd wait then set low
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}
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}
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}
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pub fn single_step(&mut self) -> Result<(), String> {
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// Execute one instruction cycle
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if let Some(cpu_component) = self.components.get_mut("cpu") {
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if let Some(cpu) = cpu_component.as_any_mut().downcast_mut::<Intel4004>() {
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// Manually advance the CPU by one cycle
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// This would require exposing cycle-level control in the CPU
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cpu.update();
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Ok(())
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} else {
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Err("Component is not an Intel4004".to_string())
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}
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} else {
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Err("CPU component not found".to_string())
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}
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}
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}
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// Trait for type erasure and downcasting
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pub trait AsAny {
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fn as_any(&self) -> &dyn std::any::Any;
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fn as_any_mut(&mut self) -> &mut dyn std::any::Any;
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}
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impl<T: 'static> AsAny for T {
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fn as_any(&self) -> &dyn std::any::Any {
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self
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}
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fn as_any_mut(&mut self) -> &mut dyn std::any::Any {
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self
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}
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}
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// CPU state for monitoring
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#[derive(Debug, Clone)]
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pub struct CpuState {
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pub program_counter: u16,
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pub accumulator: u8,
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pub carry: bool,
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pub stack_pointer: u8,
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pub cycle_count: u64,
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}
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impl Component for IntelMcs4 {
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fn name(&self) -> String {
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"Intel_MCS-4_System".to_string()
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}
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fn pins(&self) -> &HashMap<String, Arc<Mutex<Pin>>> {
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// System-level pins would include external interfaces
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// For now, return an empty map or system-level pins
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&HashMap::new()
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}
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fn get_pin(&self, name: &str) -> Result<Arc<Mutex<Pin>>, String> {
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// Delegate to appropriate component or system pins
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Err(format!("System pin {} not directly accessible", name))
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}
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fn update(&mut self) {
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if !self.is_running {
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return;
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}
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// Update all components
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for component in self.components.values_mut() {
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component.update();
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}
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}
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fn run(&mut self) {
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self.is_running = true;
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// Start all components in separate threads
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let mut handles = vec![];
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for (name, component) in self.components.iter_mut() {
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let name_clone = name.clone();
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let mut comp = component; // We need to work with the component
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// For demonstration, we'll run CPU in main thread and others in background
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if name_clone == "cpu" {
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// CPU runs in main thread for now
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} else {
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let handle = thread::spawn(move || {
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comp.run();
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});
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handles.push(handle);
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}
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}
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// Run CPU in main thread
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if let Some(cpu) = self.components.get_mut("cpu") {
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while self.is_running {
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cpu.update();
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thread::sleep(Duration::from_micros(10));
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}
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}
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// Wait for other components to stop
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for handle in handles {
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let _ = handle.join();
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}
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}
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fn stop(&mut self) {
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self.is_running = false;
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// Stop all components
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for component in self.components.values_mut() {
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component.stop();
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}
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}
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fn is_running(&self) -> bool {
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self.is_running
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}
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}
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// System monitoring and control methods
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impl IntelMcs4 {
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pub fn get_system_info(&self) -> SystemInfo {
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SystemInfo {
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cpu_speed: 750_000.0,
|
||||
rom_size: 512, // 2 × 256 bytes
|
||||
ram_size: 40, // 40 nibbles
|
||||
component_count: self.components.len(),
|
||||
}
|
||||
}
|
||||
|
||||
pub fn get_connection_graph(&self) -> Vec<Vec<String>> {
|
||||
self.connection_manager.get_connection_groups()
|
||||
}
|
||||
|
||||
pub fn load_program(&mut self, rom1_data: Vec<u8>, rom2_data: Vec<u8>) -> Result<(), String> {
|
||||
// Load program into both ROM chips
|
||||
self.load_rom_data(1, rom1_data, 0)?;
|
||||
self.load_rom_data(2, rom2_data, 0)?;
|
||||
|
||||
// Reset system to start execution
|
||||
self.reset_system();
|
||||
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
|
||||
#[derive(Debug, Clone)]
|
||||
pub struct SystemInfo {
|
||||
pub cpu_speed: f64,
|
||||
pub rom_size: usize,
|
||||
pub ram_size: usize,
|
||||
pub component_count: usize,
|
||||
}
|
||||
|
||||
#[cfg(test)]
|
||||
mod tests {
|
||||
use super::*;
|
||||
|
||||
#[test]
|
||||
fn test_mcs4_creation() {
|
||||
let system = IntelMcs4::new();
|
||||
let info = system.get_system_info();
|
||||
|
||||
assert_eq!(info.component_count, 5); // CPU, clock, RAM, 2×ROM
|
||||
assert_eq!(info.rom_size, 512);
|
||||
assert_eq!(info.ram_size, 40);
|
||||
assert!(!system.is_running());
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn test_mcs4_rom_loading() {
|
||||
let mut system = IntelMcs4::new();
|
||||
|
||||
let rom1_data = vec![0x01, 0x02, 0x03, 0x04];
|
||||
let rom2_data = vec![0x05, 0x06, 0x07, 0x08];
|
||||
|
||||
assert!(system.load_rom_data(1, rom1_data.clone(), 0).is_ok());
|
||||
assert!(system.load_rom_data(2, rom2_data.clone(), 0).is_ok());
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn test_mcs4_cpu_state() {
|
||||
let mut system = IntelMcs4::new();
|
||||
|
||||
// Set initial PC
|
||||
assert!(system.set_cpu_program_counter(0x100).is_ok());
|
||||
|
||||
let state = system.get_cpu_state().unwrap();
|
||||
assert_eq!(state.program_counter, 0x100);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn test_mcs4_system_reset() {
|
||||
let mut system = IntelMcs4::new();
|
||||
|
||||
// Set some state
|
||||
system.set_cpu_program_counter(0x123).unwrap();
|
||||
|
||||
// Reset system
|
||||
system.reset_system();
|
||||
|
||||
// Verify reset (PC should be 0 after reset)
|
||||
let state = system.get_cpu_state().unwrap();
|
||||
assert_eq!(state.program_counter, 0);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn test_mcs4_connection_graph() {
|
||||
let system = IntelMcs4::new();
|
||||
let connections = system.get_connection_graph();
|
||||
|
||||
// Should have several connection groups (data bus, control signals, etc.)
|
||||
assert!(!connections.is_empty());
|
||||
}
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue