docs: clean up completed timing plans, add VIC-20 architecture plan

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Remove 6 completed timing architecture phase plans (5-9 + overview).
Add comprehensive VIC-20 architecture plan covering:
- 6502 CPU family trait hierarchy (MOS 6502, WDC 65C02)
- Generic SRAM/ROM memory components
- 6560/6561 VIC video chip design
- 6522 VIA I/O chip design
- Address bus architecture for memory-mapped I/O
- Expansion port design
- GUI adaptations for multi-system support
- 6-phase implementation roadmap

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Jan-Peter von Hunnius 2026-05-14 21:21:46 +02:00

parent 08f53d68fe

commit 80ef0d4475

7 changed files with 1010 additions and 2709 deletions

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