More flexible bus system that takes VIC-20 address mapping and multiplexed buses like the MCS-4 into account.
Broken currently, subject to fixes
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14 changed files with 1000 additions and 68 deletions
56
src/components/memory/intel_4001.rs
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56
src/components/memory/intel_4001.rs
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use crate::components::memory::generic_rom::GenericRom;
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use crate::{Component, PinValue};
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use crate::systems::intel_mcs_4::MCS4Phase;
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// 4001 ROM: 256 bytes, 4-bit data width
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pub type Intel4001 = GenericRom<256, 4>;
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impl Intel4001 {
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fn update(&mut self) -> Result<(), String> {
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// Read the current bus phase from the pins
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let phase = self.detect_bus_phase();
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match phase {
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MCS4Phase::AddressLow => {
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self.latch_address_low();
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}
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MCS4Phase::AddressHigh => {
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self.latch_address_high();
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if self.is_selected() {
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self.prepare_data_output();
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}
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}
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MCS4Phase::DataRead => {
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if self.is_selected() {
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self.output_data();
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}
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}
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_ => {
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// Put pins in high impedance
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self.set_pins_high_z();
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}
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}
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Ok(())
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}
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fn detect_bus_phase(&self) -> MCS4Phase {
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// Detect phase based on sync and other control signals
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if let Some(sync_pin) = self.base.get_pin("pin_0") {
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match sync_pin.read() {
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PinValue::High => MCS4Phase::AddressLow, // Sync high = address phase
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PinValue::Low => MCS4Phase::DataRead, // Sync low = data phase
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_ => MCS4Phase::AddressLow,
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}
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} else {
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MCS4Phase::AddressLow
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}
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}
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fn latch_address_low(&mut self) {
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let addr_low = self.read_nibble_from_pins(9..12);
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self.latched_address = (self.latched_address & 0xFF0) | (addr_low as u16);
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}
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fn latch_address_high(&mut self) {
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let addr_high = self.read_nibble_from_pins(9..12);
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let addr_mid = self.read_nibble_from_pins(13..16);
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self.latched_address = ((addr_mid as u16) << 8) | ((addr_high as u16) << 4) | (self.latched_address & 0x00F);
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}
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}
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