Added more tests
Extracted common 400x behavior like timing and latching into common module Added maxed MCS-4
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dd93e33087
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25 changed files with 5694 additions and 494 deletions
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@ -5,6 +5,11 @@ use std::time::{Duration, Instant};
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use crate::component::{BaseComponent, Component, RunnableComponent};
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use crate::pin::{Pin, PinValue};
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use crate::components::common::intel_400x::{
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Intel400xClockHandling, Intel400xDataBus, Intel400xAddressHandling,
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Intel400xControlPins, Intel400xResetHandling, Intel400xTimingState,
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TimingState, MemoryState, RamState, utils
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};
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/// Intel 4002 - 320-bit RAM (80 nibbles × 4 bits) with integrated output ports
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/// Part of the MCS-4 family, designed to work with Intel 4004 CPU
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@ -23,6 +28,7 @@ use crate::pin::{Pin, PinValue};
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/// - Bank selection and status character handling follows Intel MCS-4 architecture
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pub struct Intel4002 {
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base: BaseComponent,
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variant: RamVariant, // RAM variant (4002-1 or 4002-2)
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memory: [u8; 80], // 80 nibbles of RAM (320 bits total) - 4 banks × 20 nibbles
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last_address: u8, // Last accessed memory address
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access_time: Duration, // RAM access latency (500ns typical)
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@ -47,16 +53,14 @@ pub struct Intel4002 {
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current_instruction: u8, // Current instruction being processed
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}
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/// RAM operation state machine states
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/// Tracks the current phase of RAM access operations
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/// Intel 4002 RAM variants
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/// - 4002-1: Standard RAM variant
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/// - 4002-2: RAM variant with different configuration
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#[derive(Debug, Clone, Copy, PartialEq)]
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enum RamState {
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Idle, // No RAM operation in progress
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AddressPhase, // Currently latching address nibbles
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WaitLatency, // Address latched, waiting for access time
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ReadData, // Reading data from RAM
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WriteData, // Writing data to RAM
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OutputPort, // Output port operation
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pub enum RamVariant {
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Type1, // 4002-1
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Type2, // 4002-2
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}
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/// Intel 4002 timing constants (based on datasheet specifications)
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@ -70,18 +74,106 @@ impl TimingConstants {
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const RAM_ACCESS: Duration = Duration::from_nanos(500); // RAM access time
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}
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impl Intel400xClockHandling for Intel4002 {
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fn get_base(&self) -> &BaseComponent {
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&self.base
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}
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}
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impl Intel400xDataBus for Intel4002 {
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fn get_base(&self) -> &BaseComponent {
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&self.base
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}
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}
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impl Intel400xAddressHandling for Intel4002 {
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fn get_base(&self) -> &BaseComponent {
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&self.base
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}
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}
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impl Intel400xControlPins for Intel4002 {
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fn get_base(&self) -> &BaseComponent {
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&self.base
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}
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}
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impl Intel400xResetHandling for Intel4002 {
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fn get_base(&self) -> &BaseComponent {
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&self.base
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}
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fn perform_reset(&self) {
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// Reset operations specific to Intel4002
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// Note: This is called from handle_reset, so we don't need to check reset pin again
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}
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}
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impl Intel400xTimingState for Intel4002 {
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fn get_timing_state(&self) -> TimingState {
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self.ram_state.into()
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}
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fn set_timing_state(&mut self, state: TimingState) {
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self.ram_state = state.into();
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}
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fn get_address_latch_time(&self) -> Option<Instant> {
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self.address_latch_time
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}
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fn set_address_latch_time(&mut self, time: Option<Instant>) {
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self.address_latch_time = time;
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}
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fn get_full_address_ready(&self) -> bool {
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self.full_address_ready
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}
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fn set_full_address_ready(&mut self, ready: bool) {
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self.full_address_ready = ready;
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}
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fn get_address_high_nibble(&self) -> Option<u8> {
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self.address_high_nibble
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}
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fn set_address_high_nibble(&mut self, nibble: Option<u8>) {
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self.address_high_nibble = nibble;
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}
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fn get_address_low_nibble(&self) -> Option<u8> {
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self.address_low_nibble
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}
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fn set_address_low_nibble(&mut self, nibble: Option<u8>) {
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self.address_low_nibble = nibble;
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}
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fn get_access_time(&self) -> Duration {
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self.access_time
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}
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}
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impl Intel4002 {
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/// Create a new Intel 4002 RAM with specified access time
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/// Parameters: name - Component identifier, access_time_ns - Memory access time in nanoseconds
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/// Returns: New Intel4002 instance with configurable access timing
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pub fn new(name: String) -> Self {
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Self::new_with_access_time(name, 500) // Default 500ns access time
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Self::new_with_variant_and_access_time(name, RamVariant::Type1, 500) // Default 500ns access time
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}
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/// Create a new Intel 4002 RAM with custom access time (for testing)
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/// Create a new Intel 4002 RAM with custom access time (for testing)
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/// Parameters: name - Component identifier, access_time_ns - Memory access time in nanoseconds
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/// Returns: New Intel4002 instance with configurable access timing
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pub fn new_with_access_time(name: String, access_time_ns: u64) -> Self {
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Self::new_with_variant_and_access_time(name, RamVariant::Type1, access_time_ns)
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}
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/// Create a new Intel 4002 RAM with specified variant and access time
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/// Parameters: name - Component identifier, variant - RAM variant (Type1 or Type2), access_time_ns - Memory access time in nanoseconds
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/// Returns: New Intel4002 instance with configurable variant and access timing
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pub fn new_with_variant_and_access_time(name: String, variant: RamVariant, access_time_ns: u64) -> Self {
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// Intel 4002 pinout (based on MCS-4 architecture):
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// - 4 data pins (D0-D3) for multiplexed address/data
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// - 4 output port pins (O0-O3)
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@ -106,8 +198,9 @@ impl Intel4002 {
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let pins = BaseComponent::create_pin_map(&pin_names, &name);
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Intel4002 {
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Intel4002 {
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base: BaseComponent::new(name, pins),
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variant,
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memory: [0u8; 80], // 80 nibbles = 4 banks × 20 nibbles each
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last_address: 0,
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access_time: Duration::from_nanos(access_time_ns),
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@ -341,21 +434,20 @@ impl Intel4002 {
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/// Handle system reset signal
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/// Hardware: RESET pin clears all internal state and tri-states outputs
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fn handle_reset(&mut self) {
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let (_, _, _, reset) = self.read_control_pins();
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if reset {
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// Hardware reset - clear all registers
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if Intel400xResetHandling::handle_reset(self, "RESET") {
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// Hardware reset - clear all registers specific to Intel4002
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self.memory = [0u8; 80]; // Clear 80 nibbles
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self.output_ports = [0u8; 4];
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self.input_latch = 0;
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self.status_characters = [0u8; 4]; // Clear 4 status character latches
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self.bank_select = 0;
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// Reset all state machines
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self.ram_state = RamState::Idle;
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self.address_latch_time = None;
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self.address_high_nibble = None;
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self.address_low_nibble = None;
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self.full_address_ready = false;
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// Reset all state machines using common functionality
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self.set_timing_state(TimingState::Idle);
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self.set_address_latch_time(None);
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self.set_address_high_nibble(None);
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self.set_address_low_nibble(None);
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self.set_full_address_ready(false);
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self.data_latch = None;
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self.instruction_phase = false;
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self.current_instruction = 0;
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@ -470,7 +562,7 @@ impl Intel4002 {
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self.handle_reset();
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// Check for RAM operation start on Φ1 rising edge with SYNC high
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let (sync, cm, p0, _) = self.read_control_pins();
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let (sync, _cm, p0, _) = self.read_control_pins();
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if sync && p0 {
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// Start RAM address phase on Φ1 rising edge
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self.start_ram_address_phase();
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@ -620,7 +712,7 @@ impl Intel4002 {
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/// Transition to data operation state
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fn start_data_operation(&mut self) {
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// Determine operation type based on control signals and address
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let (sync, cm, p0, _) = self.read_control_pins();
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let (sync, _cm, p0, _) = self.read_control_pins();
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if sync && p0 && self.full_address_ready {
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let address = self.last_address;
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@ -712,7 +804,7 @@ impl Intel4002 {
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/// Check if RAM should drive the bus
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fn should_drive_bus(&self) -> bool {
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let (sync, cm, p0, _) = self.read_control_pins();
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let (sync, _cm, p0, _) = self.read_control_pins();
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// Only drive bus during data phase when selected
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sync && p0 && self.ram_state == RamState::ReadData
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@ -741,7 +833,7 @@ impl Intel4002 {
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/// Handle instruction cycle synchronization
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fn handle_instruction_cycle(&mut self) {
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let (sync, cm, p0, _) = self.read_control_pins();
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let (sync, _cm, p0, _) = self.read_control_pins();
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if sync && self.is_phi1_rising_edge() {
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// Start of new instruction cycle
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@ -971,6 +1063,12 @@ impl Intel4002 {
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self.bank_select
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}
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/// Get the RAM variant
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/// Returns: The RAM variant (Type1 or Type2)
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pub fn get_variant(&self) -> RamVariant {
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self.variant
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}
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/// Clear all RAM to zero
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pub fn clear_ram(&mut self) {
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self.memory = [0u8; 80]; // Clear 80 nibbles
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@ -1430,7 +1528,7 @@ mod tests {
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}
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// Apply reset by calling handle_reset directly
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ram.handle_reset();
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ram.handle_reset("RESET");
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// Verify comprehensive reset
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assert_eq!(ram.read_ram(0).unwrap(), 0); // RAM cleared
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