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fix: RESET pin active-LOW and clock edge state reset

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This commit is contained in:
Jan-Peter von Hunnius 2026-02-26 11:04:25 +01:00
parent 1cf2cd6e2b
commit c9f39aa600
12 changed files with 520 additions and 327 deletions
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6
src/components/common/intel_400x.rs
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@ -294,10 +294,11 @@ pub trait Intel400xControlPins {
}
/// Read RESET pin state
/// Hardware: RESET is active LOW (pin LOW = reset active)
fn read_reset_pin(&self) -> bool {
if let Ok(pin) = self.get_base().get_pin("RESET") {
if let Ok(pin_guard) = pin.lock() {
pin_guard.read() == PinValue::High
pin_guard.read() == PinValue::Low // Active LOW: LOW means reset is active
} else {
false
}
@ -313,10 +314,11 @@ pub trait Intel400xResetHandling {
/// Handle system reset signal
/// Hardware: RESET pin clears all internal state and tri-states outputs
/// Note: RESET is active LOW (pin LOW = reset active)
fn handle_reset(&mut self, reset_pin_name: &str) -> bool {
let reset = if let Ok(pin) = self.get_base().get_pin(reset_pin_name) {
if let Ok(pin_guard) = pin.lock() {
pin_guard.read() == PinValue::High
pin_guard.read() == PinValue::Low // Active LOW: LOW means reset is active
} else {
false
}