fix: RESET pin active-LOW and clock edge state reset

src/components/memory/intel_4001.rs

@@ -95,6 +95,11 @@ impl Intel400xResetHandling for Intel4001 {
         self.io_direction = [IoDirection::Input; 4];
         self.selected_io_port = None;
         self.io_mode = IoMode::Input; // Reset I/O mode to Input
+
+        // Reset clock edge detection state to ensure proper edge detection after reset
+        // This is critical for tests that reset the chip between operations
+        self.prev_phi1 = PinValue::Low;
+        self.prev_phi2 = PinValue::Low;
     }
 }
 
@@ -1212,7 +1217,10 @@ mod tests {
 
         // Should have started memory operation and transitioned to AddressPhase
         // because SYNC=1, CM=1, CI=0 triggers chip select on PHI1 rising edge
-        assert_eq!(rom.state_machine.current_state, Intel400xUnifiedState::AddressPhase);
+        assert_eq!(
+            rom.state_machine.current_state,
+            Intel400xUnifiedState::AddressPhase
+        );
         println!(
             "Memory state after Φ1 rising: {:?}",
             rom.state_machine.current_state