fix: RESET pin active-LOW and clock edge state reset

src/components/memory/intel_4003.rs

@@ -81,6 +81,11 @@ impl Intel400xResetHandling for Intel4003 {
         self.input_buffer = 0;
         self.output_buffer = 0;
         self.serial_mode = SerialMode::Hold;
+
+        // Reset clock edge detection state to ensure proper edge detection after reset
+        // This is critical for tests that reset the chip between operations
+        self.prev_phi1 = PinValue::Low;
+        self.prev_phi2 = PinValue::Low;
     }
 }
 
@@ -367,18 +372,14 @@ impl Intel4003 {
     /// Handle Φ1 falling edge - End of address phase
     /// Hardware: Φ1 low = End of CPU address driving phase
     fn handle_phi1_falling(&mut self) {
-        // Currently no specific operations needed on Φ1 falling
-        // Address latching happens on Φ1 rising, data driving on Φ2 rising
+        // Intel 4003 ignores address transmission (responds_to_address() = false)
+        // No address latching needed for shift register operations
     }
 
     /// Handle Φ2 rising edge - Data phase
     /// Hardware: Φ2 high = Peripherals drive bus with data
     /// Focus: Data driving operations
     fn handle_phi2_rising(&mut self) {
-        println!(
-            "DEBUG: [SHIFT] Φ2 rising edge detected, current state: {:?}",
-            self.state_machine.get_state()
-        );
         // Execute current state logic
         self.execute_state_machine();
     }
@@ -388,10 +389,6 @@ impl Intel4003 {
     /// Data is held on bus during Φ2 high, tri-stated when Φ2 falls
     /// Focus: Clean up and return to idle state
     fn handle_phi2_falling(&mut self) {
-        println!(
-            "DEBUG: [SHIFT] Φ2 falling edge detected, current state: {:?}",
-            self.state_machine.get_state()
-        );
         match self.state_machine.get_state() {
             Intel400xUnifiedState::ShiftData | Intel400xUnifiedState::LoadData => {
                 // End of data phase - tri-state bus and return to idle
@@ -417,10 +414,6 @@ impl Intel4003 {
     /// Hardware: CPU provides 8-bit address as two 4-bit nibbles
     /// Note: Intel 4003 mostly ignores address transmission for shift operations
     fn handle_address_latching(&mut self) {
-        println!(
-            "DEBUG: handle_address_latching called, current state: {:?}",
-            self.state_machine.current_state
-        );
         // Intel 4003 mostly ignores address transmission for shift operations
         // But we still need to handle the address nibble for compatibility
         let nibble = self.read_data_bus() & 0x0F; // Only 4 bits are valid for address nibbles
@@ -436,18 +429,12 @@ impl Intel4003 {
     fn handle_shift_operation(&mut self) {
         // Read data from bus
         let data = self.read_data_bus() & 0x0F; // Only 4 bits are valid
-        println!("DEBUG: [SHIFT] Shifting data 0x{:X} into register", data);
 
         // Shift data into register
         self.shift_register = ((self.shift_register << 4) | (data as u16)) & 0x03FF; // Keep only 10 bits
 
         // Update output buffer with shifted-out bit
         self.output_buffer = ((self.shift_register >> 9) & 1) as u8;
-
-        println!(
-            "DEBUG: [SHIFT] Register after shift: 0x{:03X}, Output bit: {}",
-            self.shift_register, self.output_buffer
-        );
     }
 
     /// Handle shift register load operation
@@ -455,18 +442,12 @@ impl Intel4003 {
     fn handle_load_operation(&mut self) {
         // Read data from bus
         let data = self.read_data_bus() & 0x0F; // Only 4 bits are valid
-        println!("DEBUG: [SHIFT] Loading data 0x{:X} into register", data);
 
         // Load data into register
         self.shift_register = (self.shift_register & 0xFF00) | (data as u16); // Keep lower 8 bits
 
         // Update output buffer with loaded data
         self.output_buffer = data;
-
-        println!(
-            "DEBUG: [SHIFT] Register after load: 0x{:03X}, Output: 0x{:X}",
-            self.shift_register, self.output_buffer
-        );
     }
 
     /// Helper function to process latency elapsed event
@@ -549,11 +530,19 @@ impl Component for Intel4003 {
     /// Main update cycle - handles clock edge detection and operation dispatch
     /// Hardware: Responds to Φ1 and Φ2 clock edges from CPU
     fn update(&mut self) {
-        println!("DEBUG: Update called");
         if !self.is_running() {
-            println!("DEBUG: Component not running, returning");
             return;
         }
+
+        // Check for reset first (highest priority, independent of clock edges)
+        // This matches Intel 4001 behavior where reset is processed immediately
+        let reset_active = self.read_reset_pin();
+        if reset_active {
+            self.perform_reset();
+            // Skip further processing if reset is active
+            return;
+        }
+
         // Handle both rising and falling edges for proper two-phase operation
         let phi1_rising = self.is_phi1_rising_edge(self.prev_phi1);
         let phi1_falling = self.is_phi1_falling_edge(self.prev_phi1);
@@ -569,7 +558,6 @@ impl Component for Intel4003 {
         let mut events = Vec::new();
 
         if phi1_rising {
-            println!("DEBUG: phi1_rising detected");
             events.push(Intel400xEvent::ClockPhi1Rising);
         }