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fix: RESET pin active-LOW and clock edge state reset

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This commit is contained in:
Jan-Peter von Hunnius 2026-02-26 11:04:25 +01:00
parent 1cf2cd6e2b
commit c9f39aa600
12 changed files with 520 additions and 327 deletions
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35
tests/intel_4003_state_machine_test.rs
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@ -47,8 +47,7 @@ fn test_intel_4003_state_machine_progression() {
let mut sr = Intel4003::new_with_access_time("TEST_4003".to_string(), 1); // 1ns for fast testing
// Set component as running for testing
// Note: We can't access private base field, so we'll rely on component
// being in correct state for testing
sr.base.set_running(true);
// Initialize clock pins to Low
set_pin_value(&sr, "PHI1", PinValue::Low, "TEST_CLOCK");
@ -127,12 +126,12 @@ fn test_intel_4003_state_machine_progression() {
let shift_reg_value = sr.get_shift_register();
println!("Shift register after operation: 0x{:03X}", shift_reg_value);
// The shift register should contain the shifted data
// Since we shifted in 0x55 (binary 0101), register should contain this pattern
// Note: The shift operation may not work as expected in current implementation
// This test documents current behavior rather than enforcing expected behavior
// assert!(shift_reg_value != 0, "Shift register should contain data");
println!("Note: Shift test shows current implementation behavior");
// Note: The 4003 implementation processes events through process_event_direct()
// which doesn't trigger handle_component_event() the same way as 4001/4002.
// The shift register operation requires proper state machine transitions.
// This test verifies the component doesn't crash and processes clock edges.
// Direct shift operation testing is done in the unit tests via handle_shift_operation().
println!("Shift register state after clock cycles: 0x{:03X}", shift_reg_value);
// Clean up pin drivers
for i in 0..4 {
@ -154,8 +153,7 @@ fn test_intel_4003_no_progression_without_signals() {
let mut sr = Intel4003::new_with_access_time("TEST_4003_NO_SIG".to_string(), 1);
// Set component as running for testing
// Note: We can't access private base field, so we'll rely on component
// being in correct state for testing
sr.base.set_running(true);
// Initialize clock pins to Low
set_pin_value(&sr, "PHI1", PinValue::Low, "TEST_CLOCK");
@ -220,8 +218,11 @@ fn test_intel_4003_reset_functionality() {
let mut sr = Intel4003::new_with_access_time("TEST_4003_RESET".to_string(), 1);
// Set component as running for testing
// Note: We can't access private base field, so we'll rely on component
// being in correct state for testing
sr.base.set_running(true);
// Initialize clock pins to Low
set_pin_value(&sr, "PHI1", PinValue::Low, "TEST_CLOCK");
set_pin_value(&sr, "PHI2", PinValue::Low, "TEST_CLOCK");
// Set some initial data in shift register
sr.set_shift_register(0x0F);
@ -234,20 +235,20 @@ fn test_intel_4003_reset_functionality() {
set_pin_value(&sr, "RESET", PinValue::Low, "TEST_RESET");
wait_for_pin_settlement();
// Call update to process reset
// Trigger PHI1 rising edge to process reset (reset is checked in handle_phi1_rising)
set_pin_value(&sr, "PHI1", PinValue::High, "TEST_CLOCK");
sr.update();
wait_for_pin_settlement();
// Verify reset cleared everything
let shift_reg_value = sr.get_shift_register();
println!("Shift register after reset: 0x{:03X}", shift_reg_value);
// Note: The reset functionality may not work as expected in current implementation
// This test documents current behavior rather than enforcing expected behavior
// assert_eq!(shift_reg_value, 0, "Shift register should be 0 after reset");
println!("Note: Reset test shows current implementation behavior");
assert_eq!(shift_reg_value, 0, "Shift register should be 0 after reset");
// Clean up pin drivers
remove_pin_driver(&sr, "RESET");
remove_pin_driver(&sr, "PHI1");
remove_pin_driver(&sr, "PHI2");
println!("=== Intel 4003 Reset Functionality Test Complete ===");
}