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Added debug output

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Added GUI
This commit is contained in:
Jan-Peter von Hunnius 2025-10-03 11:44:55 +02:00
parent 3d4de8b268
commit e17d6ad177
18 changed files with 3137 additions and 162 deletions
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7
src/components/memory/intel_4002.rs
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@ -789,22 +789,29 @@ impl Component for Intel4002 {
self.prev_phi2 = phi2;
if phi1_rising {
println!(
"DEBUG: [RAM] Φ1 Rising Edge - State: {:?}, Ready: {}",
self.ram_state, self.full_address_ready
);
// Φ1 Rising Edge: Address phase (CPU drives bus) - handle address latching
self.handle_phi1_rising();
}
if phi1_falling {
// Φ1 Falling Edge: End of address phase
println!("DEBUG: [RAM] Φ1 Falling Edge");
self.handle_phi1_falling();
}
if phi2_rising {
// Φ2 Rising Edge: Data phase (RAM drives bus if ready) - handle data operations
println!("DEBUG: [RAM] Φ2 Rising Edge - State: {:?}", self.ram_state);
self.handle_phi2_rising();
}
if phi2_falling {
// Φ2 Falling Edge: End of data phase - tri-state bus and return to idle
println!("DEBUG: [RAM] Φ2 Falling Edge");
self.handle_phi2_falling();
}