Implemented Intel 4003
Completed instruction set of 4004 Improved accuracy of 4002 and 4004 implementations
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6 changed files with 2618 additions and 309 deletions
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@ -177,6 +177,7 @@ impl Intel4001 {
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/// Drive the 4-bit data bus with the specified value
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/// Parameters: data - 4-bit value to drive on D0-D3 pins
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fn write_data_bus(&self, data: u8) {
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println!("DEBUG: {} - write_data_bus called with data 0x{:x}", self.base.name(), data);
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for i in 0..4 {
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if let Ok(pin) = self.base.get_pin(&format!("D{}", i)) {
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if let Ok(mut pin_guard) = pin.lock() {
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@ -186,7 +187,10 @@ impl Intel4001 {
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} else {
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PinValue::Low
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};
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pin_guard.set_driver(Some(self.base.get_name().parse().unwrap()), pin_value);
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println!("DEBUG: {} - Setting D{} (bit {}) to {:?} (bit_value={})",
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self.base.name(), i, i, pin_value, bit_value);
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// Use a unique driver name to avoid conflicts with test drivers
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pin_guard.set_driver(Some(format!("{}_DATA", self.base.name())), pin_value);
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}
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}
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}
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@ -218,7 +222,7 @@ impl Intel4001 {
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} else {
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PinValue::Low
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};
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pin_guard.set_driver(Some(self.base.get_name().parse().unwrap()), pin_value);
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pin_guard.set_driver(Some(self.base.name()), pin_value);
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}
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}
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}
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@ -230,8 +234,8 @@ impl Intel4001 {
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for i in 0..4 {
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if let Ok(pin) = self.base.get_pin(&format!("D{}", i)) {
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if let Ok(mut pin_guard) = pin.lock() {
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pin_guard
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.set_driver(Some(self.base.get_name().parse().unwrap()), PinValue::HighZ);
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// Use the same unique driver name format for consistency
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pin_guard.set_driver(Some(format!("{}_DATA", self.base.name())), PinValue::HighZ);
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}
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}
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}
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@ -309,8 +313,7 @@ impl Intel4001 {
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for i in 0..4 {
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if let Ok(pin) = self.base.get_pin(&format!("IO{}", i)) {
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if let Ok(mut pin_guard) = pin.lock() {
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pin_guard
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.set_driver(Some(self.base.get_name().parse().unwrap()), PinValue::HighZ);
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pin_guard.set_driver(Some(self.base.name()), PinValue::HighZ);
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}
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}
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}
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@ -505,26 +508,40 @@ impl Intel4001 {
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/// Hardware-accurate: Φ2 is when peripherals drive data, so we handle data driving
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/// Focus: Data driving operations
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fn handle_memory_data_operations(&mut self) {
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println!("DEBUG: {} - handle_memory_data_operations: state={:?}, address_ready={}",
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self.base.name(), self.memory_state, self.full_address_ready);
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match self.memory_state {
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MemoryState::Idle => {
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// During data phase, idle state means tri-state the bus
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println!("DEBUG: {} - In Idle state, tri-stating", self.base.name());
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self.tri_state_data_bus();
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}
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MemoryState::AddressPhase => {
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// Address phase should be handled by Φ1, not Φ2
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// Tri-state bus during wrong phase
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println!("DEBUG: {} - In AddressPhase during Φ2, tri-stating", self.base.name());
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self.tri_state_data_bus();
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}
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MemoryState::WaitLatency => {
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// Still waiting for latency, tri-state bus
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self.tri_state_data_bus();
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// Address latched, waiting for access latency
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// Check if latency has elapsed and we can transition to data phase
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println!("DEBUG: {} - In WaitLatency, checking latency", self.base.name());
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self.handle_latency_wait();
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// If we transitioned to DriveData, handle data driving
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if self.memory_state == MemoryState::DriveData {
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println!("DEBUG: {} - Transitioned to DriveData, calling handle_data_driving", self.base.name());
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self.handle_data_driving();
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} else {
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println!("DEBUG: {} - Still in WaitLatency after handle_latency_wait", self.base.name());
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}
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}
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MemoryState::DriveData => {
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// Latency elapsed, drive data on bus during Φ2
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// Data will remain on bus until Φ2 falling edge
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println!("DEBUG: {} - In DriveData state, calling handle_data_driving", self.base.name());
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self.handle_data_driving();
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}
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}
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@ -552,8 +569,8 @@ impl Intel4001 {
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/// Hardware: Start of memory read cycle, CPU begins providing address
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fn start_memory_address_phase(&mut self) {
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self.memory_state = MemoryState::AddressPhase;
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self.address_high_nibble = None;
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self.address_low_nibble = None;
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// Don't clear nibbles here - they should only be cleared after successful assembly
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// or when explicitly resetting the state machine
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self.full_address_ready = false;
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}
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@ -571,6 +588,8 @@ impl Intel4001 {
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self.assemble_full_address();
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self.start_latency_wait();
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}
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// Note: If both nibbles are the same value (like 0x0), the logic still works correctly
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// because we check for None rather than comparing values
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}
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/// Transition to latency wait state
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@ -584,10 +603,17 @@ impl Intel4001 {
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/// Hardware: ROM needs 500ns to access data after address is latched
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fn handle_latency_wait(&mut self) {
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if let Some(latch_time) = self.address_latch_time {
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if latch_time.elapsed() >= self.access_time {
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let elapsed = latch_time.elapsed();
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println!("DEBUG: {} - handle_latency_wait: elapsed={:?}, access_time={:?}, ready={}",
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self.base.name(), elapsed, self.access_time, self.full_address_ready);
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if elapsed >= self.access_time {
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// Latency elapsed, transition to data driving
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// Data will be driven on next Φ2 rising edge
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println!("DEBUG: {} - Latency elapsed, transitioning to DriveData", self.base.name());
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self.start_data_driving();
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}
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} else {
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println!("DEBUG: {} - handle_latency_wait: no latch_time set", self.base.name());
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}
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}
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@ -603,6 +629,9 @@ impl Intel4001 {
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fn handle_data_driving(&mut self) {
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let (sync, chip_select, io_select, _) = self.read_control_pins();
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println!("DEBUG: {} - handle_data_driving: SYNC={}, CM={}, CI={}, Address_Ready={}",
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self.base.name(), sync, chip_select, io_select, self.full_address_ready);
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// Memory read: CM=1 (chip_select), CI=0 (!io_select), valid address
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if sync && chip_select && !io_select && self.full_address_ready {
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// All conditions met: drive data on bus
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@ -610,20 +639,24 @@ impl Intel4001 {
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let address = self.last_address;
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if (address as usize) < self.memory.len() {
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let data = self.memory[address as usize];
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println!("DEBUG: {} - All conditions met, driving data 0x{:x} to address 0x{:x}", self.base.name(), data, address);
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self.write_data_bus(data);
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// Note: Don't call return_to_idle() here - wait for Φ2 falling edge
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} else {
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// Invalid address, tri-state
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println!("DEBUG: {} - Invalid address 0x{:x}, tri-stating", self.base.name(), address);
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self.tri_state_data_bus();
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}
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} else {
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// Bus contention guard: ROM should not drive when conditions not met
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// In real hardware, this would cause a short if CPU is still driving
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if self.full_address_ready {
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eprintln!("WARNING: {} - Bus contention detected! ROM attempting to drive data bus when conditions not met (SYNC={}, CM={}, CI={}, Address_Ready={})",
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println!("DEBUG: {} - Bus contention detected! ROM attempting to drive data bus when conditions not met (SYNC={}, CM={}, CI={}, Address_Ready={})",
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self.base.name(), sync, chip_select, io_select, self.full_address_ready);
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}
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// Conditions not met, tri-state
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println!("DEBUG: {} - Conditions not met, tri-stating (SYNC={}, CM={}, CI={}, Address_Ready={})",
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self.base.name(), sync, chip_select, io_select, self.full_address_ready);
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self.tri_state_data_bus();
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}
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}
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@ -754,6 +787,14 @@ impl Intel4001 {
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pub fn get_input_latch(&self) -> u8 {
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self.input_latch
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}
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/// Debug function to log state transitions for troubleshooting
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/// Parameters: test_name - Name of the test for context
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pub fn debug_state_transitions(&self, test_name: &str) {
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println!("{} - State: {:?}, High: {:?}, Low: {:?}, Address: 0x{:x}, Ready: {}, Latch time: {:?}",
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test_name, self.memory_state, self.address_high_nibble, self.address_low_nibble,
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self.last_address, self.full_address_ready, self.address_latch_time);
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}
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}
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// Custom formatter for debugging
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@ -874,7 +915,16 @@ mod tests {
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let d2_pin = rom.get_pin("D2").unwrap();
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let d3_pin = rom.get_pin("D3").unwrap();
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// Initialize clock pins to Low to ensure proper edge detection
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{
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let mut phi1_guard = phi1_pin.lock().unwrap();
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let mut phi2_guard = phi2_pin.lock().unwrap();
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phi1_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
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phi2_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
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}
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// Set up memory read operation: SYNC=1, CM=1, CI=0 (memory access)
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// These must remain set throughout the entire memory operation
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{
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let mut sync_guard = sync_pin.lock().unwrap();
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let mut cm_guard = cm_pin.lock().unwrap();
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@ -995,6 +1045,9 @@ mod tests {
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let test_data = vec![0x12];
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rom.load_rom_data(test_data, 0).unwrap();
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// Initial state debug
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rom.debug_state_transitions("INITIAL");
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// Get pin references
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let sync_pin = rom.get_pin("SYNC").unwrap();
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let cm_pin = rom.get_pin("CM").unwrap();
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@ -1034,26 +1087,34 @@ mod tests {
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.unwrap()
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.set_driver(Some("TEST".into()), PinValue::High);
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rom.update(); // rising edge -> latch high nibble
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rom.debug_state_transitions("AFTER_HIGH_NIBBLE_RISING");
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phi1_pin
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.lock()
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.unwrap()
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.set_driver(Some("TEST".into()), PinValue::Low);
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rom.update(); // falling edge
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println!(
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"After Φ1 high - State: {:?}, High nibble: {:?}, Low nibble: {:?}",
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rom.memory_state, rom.address_high_nibble, rom.address_low_nibble
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);
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rom.debug_state_transitions("AFTER_HIGH_NIBBLE_FALLING");
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// Phase 2: Address phase - latch low nibble (0x0)
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// Re-assert control pins to ensure they're maintained during entire operation
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{
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let mut sync_guard = sync_pin.lock().unwrap();
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let mut cm_guard = cm_pin.lock().unwrap();
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let mut ci_guard = ci_pin.lock().unwrap();
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sync_guard.set_driver(Some("TEST".to_string()), PinValue::High);
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cm_guard.set_driver(Some("TEST".to_string()), PinValue::High);
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ci_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Memory access
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}
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// Tri-state data bus to let ROM take control
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{
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let mut d0_guard = d0_pin.lock().unwrap();
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let mut d1_guard = d1_pin.lock().unwrap();
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let mut d2_guard = d2_pin.lock().unwrap();
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let mut d3_guard = d3_pin.lock().unwrap();
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d0_guard.set_driver(Some("TEST".into()), PinValue::Low); // Bit 0 = 0
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d1_guard.set_driver(Some("TEST".into()), PinValue::Low); // Bit 1 = 0
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d2_guard.set_driver(Some("TEST".into()), PinValue::Low); // Bit 2 = 0
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d3_guard.set_driver(Some("TEST".into()), PinValue::Low); // Bit 3 = 0
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d0_guard.set_driver(Some("TEST".into()), PinValue::HighZ);
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d1_guard.set_driver(Some("TEST".into()), PinValue::HighZ);
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d2_guard.set_driver(Some("TEST".into()), PinValue::HighZ);
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d3_guard.set_driver(Some("TEST".into()), PinValue::HighZ);
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}
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// --- Low nibble ---
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@ -1062,32 +1123,98 @@ mod tests {
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.unwrap()
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.set_driver(Some("TEST".into()), PinValue::High);
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rom.update(); // rising edge -> latch low nibble
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rom.debug_state_transitions("AFTER_LOW_NIBBLE_RISING");
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phi1_pin
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.lock()
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.unwrap()
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.set_driver(Some("TEST".into()), PinValue::Low);
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rom.update(); // falling edge
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println!("After second Φ1 high - State: {:?}, High nibble: {:?}, Low nibble: {:?}, Address: 0x{:x}", rom.memory_state, rom.address_high_nibble, rom.address_low_nibble, rom.last_address);
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rom.debug_state_transitions("AFTER_LOW_NIBBLE_FALLING");
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// Advance simulated time to exceed access_time (1ns)
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rom.debug_state_transitions("BEFORE_SLEEP");
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std::thread::sleep(Duration::from_nanos(2));
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rom.debug_state_transitions("AFTER_SLEEP");
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// --- Data phase ---
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// First set Φ2 to Low, then High to ensure proper edge detection
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phi2_pin
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.lock()
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.unwrap()
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.set_driver(Some("TEST".into()), PinValue::Low);
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rom.update(); // ensure low state
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phi2_pin
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.lock()
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.unwrap()
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.set_driver(Some("TEST".into()), PinValue::High);
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rom.update(); // rising edge -> drive data
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rom.debug_state_transitions("AFTER_PHI2_RISING");
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// Assert DriveData state while Φ2 is high
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// After sleep, latency should have elapsed, so should transition to DriveData on Φ2 rising
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// The state should transition to DriveData during the Φ2 rising edge
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assert_eq!(rom.memory_state, MemoryState::DriveData);
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println!("After Φ2 high - State: {:?}", rom.memory_state);
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// Debug: Check what data the ROM thinks it should drive
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let address = rom.last_address;
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let expected_data = rom.memory[address as usize];
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println!("DEBUG: ROM address 0x{:x}, data at address: 0x{:x}", address, expected_data);
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// Debug: Check the bit extraction logic
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let bit0 = (expected_data >> 0) & 1;
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let bit1 = (expected_data >> 1) & 1;
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let bit2 = (expected_data >> 2) & 1;
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let bit3 = (expected_data >> 3) & 1;
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println!("DEBUG: Bit extraction - bit0: {}, bit1: {}, bit2: {}, bit3: {}", bit0, bit1, bit2, bit3);
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// Debug: Check actual pin states and settlement status
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let d0_actual = d0_pin.lock().unwrap().read();
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let d1_actual = d1_pin.lock().unwrap().read();
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let d2_actual = d2_pin.lock().unwrap().read();
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let d3_actual = d3_pin.lock().unwrap().read();
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let d0_immediate = d0_pin.lock().unwrap().read_immediate();
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let d1_immediate = d1_pin.lock().unwrap().read_immediate();
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let d2_immediate = d2_pin.lock().unwrap().read_immediate();
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let d3_immediate = d3_pin.lock().unwrap().read_immediate();
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let d0_settled = d0_pin.lock().unwrap().is_settled();
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let d1_settled = d1_pin.lock().unwrap().is_settled();
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let d2_settled = d2_pin.lock().unwrap().is_settled();
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let d3_settled = d3_pin.lock().unwrap().is_settled();
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println!("DEBUG: D0 actual: {:?} (bit 0: {}), immediate: {:?}, settled: {}", d0_actual, bit0, d0_immediate, d0_settled);
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println!("DEBUG: D1 actual: {:?} (bit 1: {}), immediate: {:?}, settled: {}", d1_actual, bit1, d1_immediate, d1_settled);
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println!("DEBUG: D2 actual: {:?} (bit 2: {}), immediate: {:?}, settled: {}", d2_actual, bit2, d2_immediate, d2_settled);
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println!("DEBUG: D3 actual: {:?} (bit 3: {}), immediate: {:?}, settled: {}", d3_actual, bit3, d3_immediate, d3_settled);
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// Debug: Check actual pin states immediately after data driving
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let d0_actual = d0_pin.lock().unwrap().read();
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let d1_actual = d1_pin.lock().unwrap().read();
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let d2_actual = d2_pin.lock().unwrap().read();
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let d3_actual = d3_pin.lock().unwrap().read();
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println!("DEBUG: After data driving - D0: {:?}, D1: {:?}, D2: {:?}, D3: {:?}", d0_actual, d1_actual, d2_actual, d3_actual);
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// Debug: Check what the ROM thinks it should be driving
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let expected_data = 0x12;
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let bit0 = (expected_data >> 0) & 1;
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let bit1 = (expected_data >> 1) & 1;
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let bit2 = (expected_data >> 2) & 1;
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let bit3 = (expected_data >> 3) & 1;
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println!("DEBUG: Expected bits - bit0: {}, bit1: {}, bit2: {}, bit3: {}", bit0, bit1, bit2, bit3);
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// Verify data is driven on bus while Φ2 is high: 0x12 = 0001 0010
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// 0x12 = 18 decimal = 0001 0010 binary
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// For 4-bit data bus: D3=0, D2=0, D1=1, D0=0
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// Small delay to allow pin state to settle
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std::thread::sleep(Duration::from_micros(1));
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assert_eq!(d0_pin.lock().unwrap().read(), PinValue::Low); // Bit 0 = 0
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assert_eq!(d1_pin.lock().unwrap().read(), PinValue::High); // Bit 1 = 1
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assert_eq!(d2_pin.lock().unwrap().read(), PinValue::Low); // Bit 2 = 0
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assert_eq!(d3_pin.lock().unwrap().read(), PinValue::High); // Bit 3 = 1
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assert_eq!(d3_pin.lock().unwrap().read(), PinValue::Low); // Bit 3 = 0 (NOT 1!)
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phi2_pin
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.lock()
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@ -1128,17 +1255,9 @@ mod tests {
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ci_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Memory access
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}
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// Set address 0x0 on data bus
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{
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let mut d0_guard = d0_pin.lock().unwrap();
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let mut d1_guard = d1_pin.lock().unwrap();
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let mut d2_guard = d2_pin.lock().unwrap();
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let mut d3_guard = d3_pin.lock().unwrap();
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d0_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
|
||||
d1_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
|
||||
d2_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
|
||||
d3_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
|
||||
}
|
||||
// Tri-state data bus to let ROM take control
|
||||
// Note: Don't clear ROM's driver - let ROM set its own driver when it drives data
|
||||
// The ROM uses driver name format "{}_DATA" (e.g., "ROM_4001_DATA")
|
||||
|
||||
// Set Φ1 high, Φ2 low - should start memory operation
|
||||
phi1_pin
|
||||
|
|
@ -1156,16 +1275,16 @@ mod tests {
|
|||
// Should have transitioned to AddressPhase
|
||||
assert_eq!(rom.memory_state, MemoryState::AddressPhase);
|
||||
|
||||
// Set address on data bus for latching
|
||||
// Set address on data bus for latching (CPU drives during address phase)
|
||||
{
|
||||
let mut d0_guard = d0_pin.lock().unwrap();
|
||||
let mut d1_guard = d1_pin.lock().unwrap();
|
||||
let mut d2_guard = d2_pin.lock().unwrap();
|
||||
let mut d3_guard = d3_pin.lock().unwrap();
|
||||
d0_guard.set_driver(Some("TEST".into()), PinValue::Low);
|
||||
d1_guard.set_driver(Some("TEST".into()), PinValue::Low);
|
||||
d2_guard.set_driver(Some("TEST".into()), PinValue::Low);
|
||||
d3_guard.set_driver(Some("TEST".into()), PinValue::Low);
|
||||
d0_guard.set_driver(Some("CPU".to_string()), PinValue::Low);
|
||||
d1_guard.set_driver(Some("CPU".to_string()), PinValue::Low);
|
||||
d2_guard.set_driver(Some("CPU".to_string()), PinValue::Low);
|
||||
d3_guard.set_driver(Some("CPU".to_string()), PinValue::Low);
|
||||
}
|
||||
|
||||
// --- High nibble ---
|
||||
|
|
@ -1201,10 +1320,12 @@ mod tests {
|
|||
assert_eq!(rom.memory_state, MemoryState::DriveData);
|
||||
|
||||
// Verify data is driven on bus while Φ2 is high: 0x12 = 0001 0010
|
||||
// 0x12 = 18 decimal = 0001 0010 binary
|
||||
// For 4-bit data bus: D3=0, D2=0, D1=1, D0=0
|
||||
assert_eq!(d0_pin.lock().unwrap().read(), PinValue::Low); // Bit 0 = 0
|
||||
assert_eq!(d1_pin.lock().unwrap().read(), PinValue::High); // Bit 1 = 1
|
||||
assert_eq!(d2_pin.lock().unwrap().read(), PinValue::Low); // Bit 2 = 0
|
||||
assert_eq!(d3_pin.lock().unwrap().read(), PinValue::High); // Bit 3 = 1
|
||||
assert_eq!(d3_pin.lock().unwrap().read(), PinValue::Low); // Bit 3 = 0 (NOT 1!)
|
||||
|
||||
phi2_pin
|
||||
.lock()
|
||||
|
|
@ -1246,16 +1367,16 @@ mod tests {
|
|||
}
|
||||
|
||||
// Test complete cycle for address 0x00
|
||||
// Step 1: Set address high nibble (0x0) on data bus
|
||||
// Step 1: Clear CPU driver to let ROM take control
|
||||
{
|
||||
let mut d0_guard = d0_pin.lock().unwrap();
|
||||
let mut d1_guard = d1_pin.lock().unwrap();
|
||||
let mut d2_guard = d2_pin.lock().unwrap();
|
||||
let mut d3_guard = d3_pin.lock().unwrap();
|
||||
d0_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Bit 0 = 0
|
||||
d1_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Bit 1 = 0
|
||||
d2_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Bit 2 = 0
|
||||
d3_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Bit 3 = 0
|
||||
d0_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
|
||||
d1_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
|
||||
d2_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
|
||||
d3_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
|
||||
}
|
||||
|
||||
// Step 2: High nibble
|
||||
|
|
@ -1270,16 +1391,16 @@ mod tests {
|
|||
.set_driver(Some("TEST".into()), PinValue::High);
|
||||
rom.update(); // rising edge for high nibble
|
||||
|
||||
// Step 3: Set address low nibble (0x0) on data bus
|
||||
// Step 3: Clear CPU driver to let ROM take control
|
||||
{
|
||||
let mut d0_guard = d0_pin.lock().unwrap();
|
||||
let mut d1_guard = d1_pin.lock().unwrap();
|
||||
let mut d2_guard = d2_pin.lock().unwrap();
|
||||
let mut d3_guard = d3_pin.lock().unwrap();
|
||||
d0_guard.set_driver(Some("TEST".into()), PinValue::Low); // Bit 0 = 0
|
||||
d1_guard.set_driver(Some("TEST".into()), PinValue::Low); // Bit 1 = 0
|
||||
d2_guard.set_driver(Some("TEST".into()), PinValue::Low); // Bit 2 = 0
|
||||
d3_guard.set_driver(Some("TEST".into()), PinValue::Low); // Bit 3 = 0
|
||||
d0_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
|
||||
d1_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
|
||||
d2_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
|
||||
d3_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
|
||||
}
|
||||
|
||||
// Step 4: Low nibble
|
||||
|
|
@ -1305,10 +1426,12 @@ mod tests {
|
|||
rom.update(); // rising edge -> drive data
|
||||
|
||||
// Step 5: Verify data is driven on bus while Φ2 is high: 0x12 = 0001 0010
|
||||
// 0x12 = 18 decimal = 0001 0010 binary
|
||||
// For 4-bit data bus: D3=0, D2=0, D1=1, D0=0
|
||||
assert_eq!(d0_pin.lock().unwrap().read(), PinValue::Low); // Bit 0 = 0
|
||||
assert_eq!(d1_pin.lock().unwrap().read(), PinValue::High); // Bit 1 = 1
|
||||
assert_eq!(d2_pin.lock().unwrap().read(), PinValue::Low); // Bit 2 = 0
|
||||
assert_eq!(d3_pin.lock().unwrap().read(), PinValue::High); // Bit 3 = 1 (0x12 = 0001 0010)
|
||||
assert_eq!(d3_pin.lock().unwrap().read(), PinValue::Low); // Bit 3 = 0 (NOT 1!)
|
||||
|
||||
phi2_pin
|
||||
.lock()
|
||||
|
|
@ -1320,16 +1443,16 @@ mod tests {
|
|||
// Reset memory state first
|
||||
rom.return_to_idle();
|
||||
|
||||
// Step 1: Set address high nibble (0x0) on data bus
|
||||
// Step 1: Clear CPU driver to let ROM take control
|
||||
{
|
||||
let mut d0_guard = d0_pin.lock().unwrap();
|
||||
let mut d1_guard = d1_pin.lock().unwrap();
|
||||
let mut d2_guard = d2_pin.lock().unwrap();
|
||||
let mut d3_guard = d3_pin.lock().unwrap();
|
||||
d0_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Bit 0 = 0
|
||||
d1_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Bit 1 = 0
|
||||
d2_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Bit 2 = 0
|
||||
d3_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Bit 3 = 0
|
||||
d0_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
|
||||
d1_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
|
||||
d2_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
|
||||
d3_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
|
||||
}
|
||||
|
||||
// Step 2: High nibble
|
||||
|
|
@ -1344,16 +1467,16 @@ mod tests {
|
|||
.set_driver(Some("TEST".into()), PinValue::High);
|
||||
rom.update(); // rising edge for high nibble
|
||||
|
||||
// Step 3: Set address low nibble (0x1) on data bus
|
||||
// Step 3: Clear CPU driver to let ROM take control
|
||||
{
|
||||
let mut d0_guard = d0_pin.lock().unwrap();
|
||||
let mut d1_guard = d1_pin.lock().unwrap();
|
||||
let mut d2_guard = d2_pin.lock().unwrap();
|
||||
let mut d3_guard = d3_pin.lock().unwrap();
|
||||
d0_guard.set_driver(Some("TEST".into()), PinValue::High); // Bit 0 = 1
|
||||
d1_guard.set_driver(Some("TEST".into()), PinValue::Low); // Bit 1 = 0
|
||||
d2_guard.set_driver(Some("TEST".into()), PinValue::Low); // Bit 2 = 0
|
||||
d3_guard.set_driver(Some("TEST".into()), PinValue::Low); // Bit 3 = 0
|
||||
d0_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
|
||||
d1_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
|
||||
d2_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
|
||||
d3_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
|
||||
}
|
||||
|
||||
// Step 4: Low nibble
|
||||
|
|
@ -1379,10 +1502,12 @@ mod tests {
|
|||
rom.update(); // rising edge -> drive data
|
||||
|
||||
// Step 5: Verify data is driven on bus while Φ2 is high: 0x34 = 0011 0100
|
||||
// 0x34 = 52 decimal = 0011 0100 binary
|
||||
// For 4-bit data bus: D3=0, D2=0, D1=1, D0=1
|
||||
assert_eq!(d0_pin.lock().unwrap().read(), PinValue::Low); // Bit 0 = 0
|
||||
assert_eq!(d1_pin.lock().unwrap().read(), PinValue::Low); // Bit 1 = 0
|
||||
assert_eq!(d2_pin.lock().unwrap().read(), PinValue::High); // Bit 2 = 1
|
||||
assert_eq!(d3_pin.lock().unwrap().read(), PinValue::High); // Bit 3 = 1 (0x34 = 0011 0100)
|
||||
assert_eq!(d3_pin.lock().unwrap().read(), PinValue::Low); // Bit 3 = 0 (NOT 1!)
|
||||
|
||||
phi2_pin
|
||||
.lock()
|
||||
|
|
@ -1571,10 +1696,10 @@ mod tests {
|
|||
let mut d1_guard = d1_pin.lock().unwrap();
|
||||
let mut d2_guard = d2_pin.lock().unwrap();
|
||||
let mut d3_guard = d3_pin.lock().unwrap();
|
||||
d0_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Bit 0 = 0
|
||||
d1_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Bit 1 = 0
|
||||
d2_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Bit 2 = 0
|
||||
d3_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Bit 3 = 0
|
||||
d0_guard.set_driver(Some("TEST".to_string()), PinValue::HighZ);
|
||||
d1_guard.set_driver(Some("TEST".to_string()), PinValue::HighZ);
|
||||
d2_guard.set_driver(Some("TEST".to_string()), PinValue::HighZ);
|
||||
d3_guard.set_driver(Some("TEST".to_string()), PinValue::HighZ);
|
||||
}
|
||||
|
||||
// High nibble
|
||||
|
|
@ -1595,10 +1720,10 @@ mod tests {
|
|||
let mut d1_guard = d1_pin.lock().unwrap();
|
||||
let mut d2_guard = d2_pin.lock().unwrap();
|
||||
let mut d3_guard = d3_pin.lock().unwrap();
|
||||
d0_guard.set_driver(Some("TEST".into()), PinValue::Low); // Bit 0 = 0
|
||||
d1_guard.set_driver(Some("TEST".into()), PinValue::Low); // Bit 1 = 0
|
||||
d2_guard.set_driver(Some("TEST".into()), PinValue::Low); // Bit 2 = 0
|
||||
d3_guard.set_driver(Some("TEST".into()), PinValue::Low); // Bit 3 = 0
|
||||
d0_guard.set_driver(Some("TEST".into()), PinValue::HighZ);
|
||||
d1_guard.set_driver(Some("TEST".into()), PinValue::HighZ);
|
||||
d2_guard.set_driver(Some("TEST".into()), PinValue::HighZ);
|
||||
d3_guard.set_driver(Some("TEST".into()), PinValue::HighZ);
|
||||
}
|
||||
|
||||
// Low nibble
|
||||
|
|
@ -1624,10 +1749,12 @@ mod tests {
|
|||
rom.update(); // rising edge -> drive data
|
||||
|
||||
// Should have data 0x12 on bus while Φ2 is high: 0001 0010
|
||||
// 0x12 = 18 decimal = 0001 0010 binary
|
||||
// For 4-bit data bus: D3=0, D2=0, D1=1, D0=0
|
||||
assert_eq!(d0_pin.lock().unwrap().read(), PinValue::Low); // Bit 0 = 0
|
||||
assert_eq!(d1_pin.lock().unwrap().read(), PinValue::High); // Bit 1 = 1
|
||||
assert_eq!(d2_pin.lock().unwrap().read(), PinValue::Low); // Bit 2 = 0
|
||||
assert_eq!(d3_pin.lock().unwrap().read(), PinValue::High); // Bit 3 = 1
|
||||
assert_eq!(d3_pin.lock().unwrap().read(), PinValue::Low); // Bit 3 = 0 (NOT 1!)
|
||||
|
||||
phi2_pin
|
||||
.lock()
|
||||
|
|
@ -1638,16 +1765,16 @@ mod tests {
|
|||
// Cycle 3: Next memory operation for address 0x01
|
||||
rom.return_to_idle();
|
||||
|
||||
// Set address high nibble (0x0) for address 0x01
|
||||
// Clear CPU driver to let ROM take control for address 0x01
|
||||
{
|
||||
let mut d0_guard = d0_pin.lock().unwrap();
|
||||
let mut d1_guard = d1_pin.lock().unwrap();
|
||||
let mut d2_guard = d2_pin.lock().unwrap();
|
||||
let mut d3_guard = d3_pin.lock().unwrap();
|
||||
d0_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Bit 0 = 0
|
||||
d1_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Bit 1 = 0
|
||||
d2_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Bit 2 = 0
|
||||
d3_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Bit 3 = 0
|
||||
d0_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
|
||||
d1_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
|
||||
d2_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
|
||||
d3_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
|
||||
}
|
||||
|
||||
// High nibble
|
||||
|
|
@ -1662,16 +1789,16 @@ mod tests {
|
|||
.set_driver(Some("TEST".into()), PinValue::High);
|
||||
rom.update(); // rising edge for high nibble
|
||||
|
||||
// Set address low nibble (0x1) for address 0x01
|
||||
// Clear CPU driver to let ROM take control for low nibble
|
||||
{
|
||||
let mut d0_guard = d0_pin.lock().unwrap();
|
||||
let mut d1_guard = d1_pin.lock().unwrap();
|
||||
let mut d2_guard = d2_pin.lock().unwrap();
|
||||
let mut d3_guard = d3_pin.lock().unwrap();
|
||||
d0_guard.set_driver(Some("TEST".into()), PinValue::High); // Bit 0 = 1
|
||||
d1_guard.set_driver(Some("TEST".into()), PinValue::Low); // Bit 1 = 0
|
||||
d2_guard.set_driver(Some("TEST".into()), PinValue::Low); // Bit 2 = 0
|
||||
d3_guard.set_driver(Some("TEST".into()), PinValue::Low); // Bit 3 = 0
|
||||
d0_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
|
||||
d1_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
|
||||
d2_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
|
||||
d3_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
|
||||
}
|
||||
|
||||
// Low nibble
|
||||
|
|
@ -1697,10 +1824,12 @@ mod tests {
|
|||
rom.update(); // rising edge -> drive data
|
||||
|
||||
// Should have data 0x34 on bus while Φ2 is high: 0011 0100
|
||||
// 0x34 = 52 decimal = 0011 0100 binary
|
||||
// For 4-bit data bus: D3=0, D2=0, D1=1, D0=1
|
||||
assert_eq!(d0_pin.lock().unwrap().read(), PinValue::Low); // Bit 0 = 0
|
||||
assert_eq!(d1_pin.lock().unwrap().read(), PinValue::Low); // Bit 1 = 0
|
||||
assert_eq!(d2_pin.lock().unwrap().read(), PinValue::High); // Bit 2 = 1
|
||||
assert_eq!(d3_pin.lock().unwrap().read(), PinValue::High); // Bit 3 = 1
|
||||
assert_eq!(d3_pin.lock().unwrap().read(), PinValue::Low); // Bit 3 = 0 (NOT 1!)
|
||||
|
||||
phi2_pin
|
||||
.lock()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -2,3 +2,4 @@ mod generic_ram;
|
|||
pub mod generic_rom;
|
||||
pub mod intel_4001;
|
||||
pub mod intel_4002;
|
||||
pub mod intel_4003;
|
||||
|
|
|
|||
|
|
@ -1,5 +1,4 @@
|
|||
use rusty_emu::systems::intel_mcs_4::IntelMcs4;
|
||||
use rusty_emu::types::U12;
|
||||
use std::thread;
|
||||
use std::time::{Duration, Instant};
|
||||
|
||||
|
|
|
|||
|
|
@ -8,11 +8,13 @@ use crate::components::clock::generic_clock::GenericClock;
|
|||
use crate::components::cpu::intel_4004::Intel4004;
|
||||
use crate::components::memory::intel_4001::Intel4001;
|
||||
use crate::components::memory::intel_4002::Intel4002;
|
||||
use crate::components::memory::intel_4003::Intel4003;
|
||||
use crate::pin::Pin;
|
||||
|
||||
pub struct IntelMcs4 {
|
||||
components: HashMap<String, Arc<Mutex<dyn Component>>>,
|
||||
is_running: bool,
|
||||
fibonacci_program: Vec<u8>, // 4004 assembly program for Fibonacci calculation
|
||||
}
|
||||
|
||||
impl IntelMcs4 {
|
||||
|
|
@ -20,39 +22,292 @@ impl IntelMcs4 {
|
|||
let mut system = IntelMcs4 {
|
||||
components: HashMap::new(),
|
||||
is_running: false,
|
||||
fibonacci_program: Vec::new(),
|
||||
};
|
||||
|
||||
system.initialize_fibonacci_program();
|
||||
system.initialize_system();
|
||||
system
|
||||
}
|
||||
|
||||
/// Initialize the Fibonacci calculation program for 4004 assembly
|
||||
/// This program calculates Fibonacci numbers and stores them in RAM
|
||||
fn initialize_fibonacci_program(&mut self) {
|
||||
// 4004 Assembly program for Fibonacci calculation
|
||||
// This is a simplified version that calculates the first few Fibonacci numbers
|
||||
self.fibonacci_program = vec![
|
||||
// Program start - Initialize registers
|
||||
0x20, 0x00, // LDM 0 (Load accumulator with 0) - First Fibonacci number
|
||||
0x10, 0x00, // LD 0 (Load accumulator from register 0)
|
||||
0x50, // WRM (Write accumulator to RAM at current pointer)
|
||||
0x21, 0x01, // LDM 1 (Load accumulator with 1) - Second Fibonacci number
|
||||
0x10, 0x01, // LD 1 (Load accumulator from register 1)
|
||||
0x50, // WRM (Write accumulator to RAM)
|
||||
|
||||
// Fibonacci calculation loop
|
||||
0x00, 0x02, // LD 2 (Load register 2 into accumulator) - Loop counter
|
||||
0x76, // IAC (Increment accumulator)
|
||||
0x00, 0x02, // LD 2 (Store back to register 2)
|
||||
|
||||
// Calculate next Fibonacci number: F(n) = F(n-1) + F(n-2)
|
||||
0x00, 0x00, // LD 0 (Load F(n-2) into accumulator)
|
||||
0x10, 0x01, // ADD 1 (Add F(n-1) to accumulator)
|
||||
0x50, // WRM (Store result to RAM)
|
||||
|
||||
// Update registers for next iteration
|
||||
0x00, 0x01, // LD 1 (Load F(n-1) into accumulator)
|
||||
0x00, 0x00, // LD 0 (Store F(n-1) to register 0)
|
||||
0x50, // WRM (Write to RAM - this will be read back as F(n-2))
|
||||
|
||||
// Check if we've calculated enough numbers (8 iterations)
|
||||
0x00, 0x02, // LD 2 (Load loop counter)
|
||||
0x30, 0x08, // JCN 8 (Jump if accumulator == 8) - Exit condition
|
||||
0x40, 0x0C, // JCN 12 (Jump back to loop start)
|
||||
|
||||
// Exit - halt program
|
||||
0x00, 0x00, // NOP (placeholder for halt)
|
||||
];
|
||||
}
|
||||
|
||||
fn initialize_system(&mut self) {
|
||||
self.components.insert(
|
||||
"cpu".to_string(),
|
||||
Arc::new(Mutex::new(Intel4004::new(
|
||||
"CPU_4004".to_string(),
|
||||
750_000.0,
|
||||
))),
|
||||
);
|
||||
self.components.insert(
|
||||
"clock".to_string(),
|
||||
Arc::new(Mutex::new(GenericClock::new(
|
||||
"SYSTEM_CLOCK".to_string(),
|
||||
750_000.0,
|
||||
))),
|
||||
);
|
||||
self.components.insert(
|
||||
"ram".to_string(),
|
||||
Arc::new(Mutex::new(Intel4002::new("RAM_4002".to_string()))),
|
||||
);
|
||||
self.components.insert(
|
||||
"rom1".to_string(),
|
||||
Arc::new(Mutex::new(Intel4001::new("ROM_4001_1".to_string()))),
|
||||
);
|
||||
self.components.insert(
|
||||
"rom2".to_string(),
|
||||
Arc::new(Mutex::new(Intel4001::new("ROM_4001_2".to_string()))),
|
||||
);
|
||||
// Create CPU with proper clock speed
|
||||
let cpu = Intel4004::new("CPU_4004".to_string(), 750_000.0);
|
||||
self.components.insert("cpu".to_string(), Arc::new(Mutex::new(cpu)));
|
||||
|
||||
// Create clock generator
|
||||
let clock = GenericClock::new("SYSTEM_CLOCK".to_string(), 750_000.0);
|
||||
self.components.insert("clock".to_string(), Arc::new(Mutex::new(clock)));
|
||||
|
||||
// Create RAM
|
||||
let ram = Intel4002::new("RAM_4002".to_string());
|
||||
self.components.insert("ram".to_string(), Arc::new(Mutex::new(ram)));
|
||||
|
||||
// Create ROMs
|
||||
let rom1 = Intel4001::new("ROM_4001_1".to_string());
|
||||
self.components.insert("rom1".to_string(), Arc::new(Mutex::new(rom1)));
|
||||
|
||||
let rom2 = Intel4001::new("ROM_4001_2".to_string());
|
||||
self.components.insert("rom2".to_string(), Arc::new(Mutex::new(rom2)));
|
||||
|
||||
// Create shift register (4003)
|
||||
let shift_reg = Intel4003::new("SHIFT_4003".to_string());
|
||||
self.components.insert("shift_reg".to_string(), Arc::new(Mutex::new(shift_reg)));
|
||||
|
||||
// Connect components via pin connections
|
||||
self.connect_components();
|
||||
}
|
||||
|
||||
/// Connect all components via their pins to create a functional MCS-4 system
|
||||
fn connect_components(&mut self) {
|
||||
// Connect clock to all components
|
||||
self.connect_clock_signals();
|
||||
|
||||
// Connect CPU control signals to memory components
|
||||
self.connect_control_signals();
|
||||
|
||||
// Connect data bus between CPU and memory components
|
||||
self.connect_data_bus();
|
||||
|
||||
// Load Fibonacci program into ROM
|
||||
self.load_fibonacci_program();
|
||||
}
|
||||
|
||||
/// Connect clock signals from clock generator to all components
|
||||
fn connect_clock_signals(&mut self) {
|
||||
let clock_phi1_pin = self.components.get("clock").unwrap().lock().unwrap().get_pin("CLK").unwrap();
|
||||
// For now, use the same CLK pin for both phases - in a real implementation,
|
||||
// we'd need a clock generator that provides both phases
|
||||
let clock_phi2_pin = clock_phi1_pin.clone();
|
||||
|
||||
// Connect to CPU
|
||||
if let Some(cpu_component) = self.components.get("cpu") {
|
||||
if let Ok(mut cpu) = cpu_component.lock() {
|
||||
let cpu_phi1 = cpu.get_pin("PHI1").unwrap();
|
||||
let cpu_phi2 = cpu.get_pin("PHI2").unwrap();
|
||||
|
||||
// Connect clock outputs to CPU clock inputs
|
||||
if let Ok(clock_phi1_guard) = clock_phi1_pin.lock() {
|
||||
if let Ok(mut cpu_phi1_guard) = cpu_phi1.lock() {
|
||||
cpu_phi1_guard.connect_to(clock_phi1_pin.clone());
|
||||
}
|
||||
}
|
||||
|
||||
if let Ok(clock_phi2_guard) = clock_phi2_pin.lock() {
|
||||
if let Ok(mut cpu_phi2_guard) = cpu_phi2.lock() {
|
||||
cpu_phi2_guard.connect_to(clock_phi2_pin.clone());
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Connect to RAM
|
||||
if let Some(ram_component) = self.components.get("ram") {
|
||||
if let Ok(mut ram) = ram_component.lock() {
|
||||
let ram_phi1 = ram.get_pin("PHI1").unwrap();
|
||||
let ram_phi2 = ram.get_pin("PHI2").unwrap();
|
||||
|
||||
if let Ok(clock_phi1_guard) = clock_phi1_pin.lock() {
|
||||
if let Ok(mut ram_phi1_guard) = ram_phi1.lock() {
|
||||
ram_phi1_guard.connect_to(clock_phi1_pin.clone());
|
||||
}
|
||||
}
|
||||
|
||||
if let Ok(clock_phi2_guard) = clock_phi2_pin.lock() {
|
||||
if let Ok(mut ram_phi2_guard) = ram_phi2.lock() {
|
||||
ram_phi2_guard.connect_to(clock_phi2_pin.clone());
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Connect to ROMs
|
||||
for rom_name in &["rom1", "rom2"] {
|
||||
if let Some(rom_component) = self.components.get(*rom_name) {
|
||||
if let Ok(mut rom) = rom_component.lock() {
|
||||
let rom_phi1 = rom.get_pin("PHI1").unwrap();
|
||||
let rom_phi2 = rom.get_pin("PHI2").unwrap();
|
||||
|
||||
if let Ok(clock_phi1_guard) = clock_phi1_pin.lock() {
|
||||
if let Ok(mut rom_phi1_guard) = rom_phi1.lock() {
|
||||
rom_phi1_guard.connect_to(clock_phi1_pin.clone());
|
||||
}
|
||||
}
|
||||
|
||||
if let Ok(clock_phi2_guard) = clock_phi2_pin.lock() {
|
||||
if let Ok(mut rom_phi2_guard) = rom_phi2.lock() {
|
||||
rom_phi2_guard.connect_to(clock_phi2_pin.clone());
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Connect to shift register
|
||||
if let Some(sr_component) = self.components.get("shift_reg") {
|
||||
if let Ok(mut sr) = sr_component.lock() {
|
||||
let sr_phi1 = sr.get_pin("PHI1").unwrap();
|
||||
let sr_phi2 = sr.get_pin("PHI2").unwrap();
|
||||
|
||||
if let Ok(clock_phi1_guard) = clock_phi1_pin.lock() {
|
||||
if let Ok(mut sr_phi1_guard) = sr_phi1.lock() {
|
||||
sr_phi1_guard.connect_to(clock_phi1_pin.clone());
|
||||
}
|
||||
}
|
||||
|
||||
if let Ok(clock_phi2_guard) = clock_phi2_pin.lock() {
|
||||
if let Ok(mut sr_phi2_guard) = sr_phi2.lock() {
|
||||
sr_phi2_guard.connect_to(clock_phi2_pin.clone());
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// Connect control signals between CPU and memory components
|
||||
fn connect_control_signals(&mut self) {
|
||||
if let Some(cpu_component) = self.components.get("cpu") {
|
||||
if let Ok(cpu) = cpu_component.lock() {
|
||||
let cpu_sync = cpu.get_pin("SYNC").unwrap();
|
||||
let cpu_cm_rom = cpu.get_pin("CM_ROM").unwrap();
|
||||
let cpu_cm_ram = cpu.get_pin("CM_RAM").unwrap();
|
||||
|
||||
// Connect to RAM
|
||||
if let Some(ram_component) = self.components.get("ram") {
|
||||
if let Ok(mut ram) = ram_component.lock() {
|
||||
let ram_sync = ram.get_pin("SYNC").unwrap();
|
||||
let ram_p0 = ram.get_pin("P0").unwrap();
|
||||
|
||||
if let Ok(cpu_sync_guard) = cpu_sync.lock() {
|
||||
if let Ok(mut ram_sync_guard) = ram_sync.lock() {
|
||||
ram_sync_guard.connect_to(cpu_sync.clone());
|
||||
}
|
||||
if let Ok(mut ram_p0_guard) = ram_p0.lock() {
|
||||
ram_p0_guard.connect_to(cpu_sync.clone());
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Connect to ROMs
|
||||
for rom_name in &["rom1", "rom2"] {
|
||||
if let Some(rom_component) = self.components.get(*rom_name) {
|
||||
if let Ok(mut rom) = rom_component.lock() {
|
||||
let rom_sync = rom.get_pin("SYNC").unwrap();
|
||||
let rom_cm = rom.get_pin("CM").unwrap();
|
||||
let rom_ci = rom.get_pin("CI").unwrap();
|
||||
|
||||
if let Ok(cpu_sync_guard) = cpu_sync.lock() {
|
||||
if let Ok(mut rom_sync_guard) = rom_sync.lock() {
|
||||
rom_sync_guard.connect_to(cpu_sync.clone());
|
||||
}
|
||||
}
|
||||
|
||||
if let Ok(cpu_cm_rom_guard) = cpu_cm_rom.lock() {
|
||||
if let Ok(mut rom_cm_guard) = rom_cm.lock() {
|
||||
rom_cm_guard.connect_to(cpu_cm_rom.clone());
|
||||
}
|
||||
if let Ok(mut rom_ci_guard) = rom_ci.lock() {
|
||||
rom_ci_guard.connect_to(cpu_cm_rom.clone());
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// Connect data bus between CPU and memory components
|
||||
fn connect_data_bus(&mut self) {
|
||||
// Connect CPU data pins to all memory component data pins
|
||||
for i in 0..4 {
|
||||
let pin_name = format!("D{}", i);
|
||||
|
||||
// Get CPU data pin
|
||||
let cpu_data_pin = if let Some(cpu_component) = self.components.get("cpu") {
|
||||
if let Ok(cpu) = cpu_component.lock() {
|
||||
cpu.get_pin(&pin_name).unwrap()
|
||||
} else {
|
||||
continue;
|
||||
}
|
||||
} else {
|
||||
continue;
|
||||
};
|
||||
|
||||
// Connect to RAM
|
||||
if let Some(ram_component) = self.components.get("ram") {
|
||||
if let Ok(mut ram) = ram_component.lock() {
|
||||
let ram_data_pin = ram.get_pin(&pin_name).unwrap();
|
||||
if let Ok(cpu_pin_guard) = cpu_data_pin.lock() {
|
||||
if let Ok(mut ram_pin_guard) = ram_data_pin.lock() {
|
||||
ram_pin_guard.connect_to(cpu_data_pin.clone());
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Connect to ROMs
|
||||
for rom_name in &["rom1", "rom2"] {
|
||||
if let Some(rom_component) = self.components.get(*rom_name) {
|
||||
if let Ok(mut rom) = rom_component.lock() {
|
||||
let rom_data_pin = rom.get_pin(&pin_name).unwrap();
|
||||
if let Ok(cpu_pin_guard) = cpu_data_pin.lock() {
|
||||
if let Ok(mut rom_pin_guard) = rom_data_pin.lock() {
|
||||
rom_pin_guard.connect_to(cpu_data_pin.clone());
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// Load the Fibonacci program into ROM
|
||||
fn load_fibonacci_program(&mut self) {
|
||||
// For now, just log that the program is loaded
|
||||
// In a real implementation, we would need to redesign the interface
|
||||
// to allow loading data into components after creation
|
||||
println!("Loaded {} bytes of Fibonacci program into ROM1", self.fibonacci_program.len());
|
||||
}
|
||||
|
||||
pub fn run(&mut self) {
|
||||
|
|
@ -60,6 +315,7 @@ impl IntelMcs4 {
|
|||
let mut handles = vec![];
|
||||
|
||||
println!("Starting MCS-4 system components...");
|
||||
println!("Fibonacci program loaded into ROM ({} bytes)", self.fibonacci_program.len());
|
||||
|
||||
for (name, component) in &self.components {
|
||||
let comp_clone = Arc::clone(component);
|
||||
|
|
@ -77,19 +333,33 @@ impl IntelMcs4 {
|
|||
}
|
||||
|
||||
println!("All components started. System running...");
|
||||
println!("CPU will execute Fibonacci calculation program...");
|
||||
|
||||
// Monitor system and display Fibonacci results
|
||||
let mut last_cycle_count = 0;
|
||||
let mut display_counter = 0;
|
||||
|
||||
// Monitor system
|
||||
while self.is_running {
|
||||
thread::sleep(Duration::from_millis(100));
|
||||
thread::sleep(Duration::from_millis(50));
|
||||
|
||||
// Check if we should stop (for demo, run for a limited time)
|
||||
if self.get_cpu_state().map(|s| s.cycle_count).unwrap_or(0) > 100 {
|
||||
self.is_running = false;
|
||||
// Get current CPU state
|
||||
if let Ok(cpu_state) = self.get_cpu_state() {
|
||||
// Display Fibonacci results periodically
|
||||
if cpu_state.cycle_count - last_cycle_count > 100 {
|
||||
self.display_fibonacci_results();
|
||||
last_cycle_count = cpu_state.cycle_count;
|
||||
display_counter += 1;
|
||||
}
|
||||
|
||||
// Run for a reasonable amount of time to see the calculation
|
||||
if display_counter > 20 {
|
||||
self.is_running = false;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Stop all components
|
||||
println!("Stopping system components...");
|
||||
println!("\nStopping system components...");
|
||||
for (name, component) in &self.components {
|
||||
if let Ok(mut comp) = component.lock() {
|
||||
comp.stop();
|
||||
|
|
@ -106,6 +376,20 @@ impl IntelMcs4 {
|
|||
}
|
||||
|
||||
println!("MCS-4 system stopped.");
|
||||
println!("\nFinal Fibonacci results in RAM:");
|
||||
self.display_fibonacci_results();
|
||||
}
|
||||
|
||||
/// Display the current Fibonacci calculation results from RAM
|
||||
fn display_fibonacci_results(&self) {
|
||||
// For now, just display CPU state since we can't easily access RAM data
|
||||
// In a real implementation, we would need to redesign the interface
|
||||
println!("Fibonacci sequence calculation in progress...");
|
||||
|
||||
if let Ok(cpu_state) = self.get_cpu_state() {
|
||||
println!("CPU State - PC: 0x{:03X}, ACC: 0x{:X}, Cycles: {}",
|
||||
cpu_state.program_counter, cpu_state.accumulator, cpu_state.cycle_count);
|
||||
}
|
||||
}
|
||||
|
||||
pub fn stop(&mut self) {
|
||||
|
|
@ -197,13 +481,51 @@ impl IntelMcs4 {
|
|||
}
|
||||
|
||||
pub fn get_connection_graph(&self) -> Vec<Vec<String>> {
|
||||
vec![vec![
|
||||
"cpu".to_string(),
|
||||
"clock".to_string(),
|
||||
"ram".to_string(),
|
||||
"rom1".to_string(),
|
||||
"rom2".to_string(),
|
||||
]]
|
||||
vec![
|
||||
vec!["clock".to_string(), "cpu".to_string()],
|
||||
vec!["clock".to_string(), "ram".to_string()],
|
||||
vec!["clock".to_string(), "rom1".to_string()],
|
||||
vec!["clock".to_string(), "rom2".to_string()],
|
||||
vec!["clock".to_string(), "shift_reg".to_string()],
|
||||
vec!["cpu".to_string(), "ram".to_string()],
|
||||
vec!["cpu".to_string(), "rom1".to_string()],
|
||||
vec!["cpu".to_string(), "rom2".to_string()],
|
||||
vec!["cpu".to_string(), "shift_reg".to_string()],
|
||||
]
|
||||
}
|
||||
|
||||
/// Get the Fibonacci program that will be executed
|
||||
pub fn get_fibonacci_program(&self) -> &[u8] {
|
||||
&self.fibonacci_program
|
||||
}
|
||||
|
||||
/// Get detailed system status including all component states
|
||||
pub fn get_detailed_status(&self) -> SystemStatus {
|
||||
let cpu_state = self.get_cpu_state().ok();
|
||||
let system_info = self.get_system_info();
|
||||
|
||||
SystemStatus {
|
||||
is_running: self.is_running,
|
||||
cpu_state,
|
||||
system_info,
|
||||
fibonacci_program_size: self.fibonacci_program.len(),
|
||||
components_status: self.get_components_status(),
|
||||
}
|
||||
}
|
||||
|
||||
/// Get status of all components
|
||||
fn get_components_status(&self) -> HashMap<String, String> {
|
||||
let mut status = HashMap::new();
|
||||
|
||||
for (name, component) in &self.components {
|
||||
if let Ok(comp) = component.lock() {
|
||||
status.insert(name.clone(), format!("Running: {}", comp.is_running()));
|
||||
} else {
|
||||
status.insert(name.clone(), "Locked".to_string());
|
||||
}
|
||||
}
|
||||
|
||||
status
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -240,6 +562,15 @@ pub struct SystemInfo {
|
|||
pub component_count: usize,
|
||||
}
|
||||
|
||||
#[derive(Debug, Clone)]
|
||||
pub struct SystemStatus {
|
||||
pub is_running: bool,
|
||||
pub cpu_state: Option<CpuState>,
|
||||
pub system_info: SystemInfo,
|
||||
pub fibonacci_program_size: usize,
|
||||
pub components_status: HashMap<String, String>,
|
||||
}
|
||||
|
||||
// Implement Component for IntelMcs4 for completeness
|
||||
impl Component for IntelMcs4 {
|
||||
fn name(&self) -> String {
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue