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Implemented Intel 4003

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Completed instruction set of 4004
Improved accuracy of 4002 and 4004 implementations
This commit is contained in:
Jan-Peter von Hunnius 2025-09-28 20:31:12 +02:00
parent 5bc1916b2f
commit e7c98f0c47
6 changed files with 2618 additions and 309 deletions
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958
src/components/cpu/intel_4004.rs
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293
src/components/memory/intel_4001.rs
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@ -177,6 +177,7 @@ impl Intel4001 {
/// Drive the 4-bit data bus with the specified value
/// Parameters: data - 4-bit value to drive on D0-D3 pins
fn write_data_bus(&self, data: u8) {
println!("DEBUG: {} - write_data_bus called with data 0x{:x}", self.base.name(), data);
for i in 0..4 {
if let Ok(pin) = self.base.get_pin(&format!("D{}", i)) {
if let Ok(mut pin_guard) = pin.lock() {
@ -186,7 +187,10 @@ impl Intel4001 {
} else {
PinValue::Low
};
pin_guard.set_driver(Some(self.base.get_name().parse().unwrap()), pin_value);
println!("DEBUG: {} - Setting D{} (bit {}) to {:?} (bit_value={})",
self.base.name(), i, i, pin_value, bit_value);
// Use a unique driver name to avoid conflicts with test drivers
pin_guard.set_driver(Some(format!("{}_DATA", self.base.name())), pin_value);
}
}
}
@ -218,7 +222,7 @@ impl Intel4001 {
} else {
PinValue::Low
};
pin_guard.set_driver(Some(self.base.get_name().parse().unwrap()), pin_value);
pin_guard.set_driver(Some(self.base.name()), pin_value);
}
}
}
@ -230,8 +234,8 @@ impl Intel4001 {
for i in 0..4 {
if let Ok(pin) = self.base.get_pin(&format!("D{}", i)) {
if let Ok(mut pin_guard) = pin.lock() {
pin_guard
.set_driver(Some(self.base.get_name().parse().unwrap()), PinValue::HighZ);
// Use the same unique driver name format for consistency
pin_guard.set_driver(Some(format!("{}_DATA", self.base.name())), PinValue::HighZ);
}
}
}
@ -309,8 +313,7 @@ impl Intel4001 {
for i in 0..4 {
if let Ok(pin) = self.base.get_pin(&format!("IO{}", i)) {
if let Ok(mut pin_guard) = pin.lock() {
pin_guard
.set_driver(Some(self.base.get_name().parse().unwrap()), PinValue::HighZ);
pin_guard.set_driver(Some(self.base.name()), PinValue::HighZ);
}
}
}
@ -505,26 +508,40 @@ impl Intel4001 {
/// Hardware-accurate: Φ2 is when peripherals drive data, so we handle data driving
/// Focus: Data driving operations
fn handle_memory_data_operations(&mut self) {
println!("DEBUG: {} - handle_memory_data_operations: state={:?}, address_ready={}",
self.base.name(), self.memory_state, self.full_address_ready);
match self.memory_state {
MemoryState::Idle => {
// During data phase, idle state means tri-state the bus
println!("DEBUG: {} - In Idle state, tri-stating", self.base.name());
self.tri_state_data_bus();
}
MemoryState::AddressPhase => {
// Address phase should be handled by Φ1, not Φ2
// Tri-state bus during wrong phase
println!("DEBUG: {} - In AddressPhase during Φ2, tri-stating", self.base.name());
self.tri_state_data_bus();
}
MemoryState::WaitLatency => {
// Still waiting for latency, tri-state bus
self.tri_state_data_bus();
// Address latched, waiting for access latency
// Check if latency has elapsed and we can transition to data phase
println!("DEBUG: {} - In WaitLatency, checking latency", self.base.name());
self.handle_latency_wait();
// If we transitioned to DriveData, handle data driving
if self.memory_state == MemoryState::DriveData {
println!("DEBUG: {} - Transitioned to DriveData, calling handle_data_driving", self.base.name());
self.handle_data_driving();
} else {
println!("DEBUG: {} - Still in WaitLatency after handle_latency_wait", self.base.name());
}
}
MemoryState::DriveData => {
// Latency elapsed, drive data on bus during Φ2
// Data will remain on bus until Φ2 falling edge
println!("DEBUG: {} - In DriveData state, calling handle_data_driving", self.base.name());
self.handle_data_driving();
}
}
@ -552,8 +569,8 @@ impl Intel4001 {
/// Hardware: Start of memory read cycle, CPU begins providing address
fn start_memory_address_phase(&mut self) {
self.memory_state = MemoryState::AddressPhase;
self.address_high_nibble = None;
self.address_low_nibble = None;
// Don't clear nibbles here - they should only be cleared after successful assembly
// or when explicitly resetting the state machine
self.full_address_ready = false;
}
@ -571,6 +588,8 @@ impl Intel4001 {
self.assemble_full_address();
self.start_latency_wait();
}
// Note: If both nibbles are the same value (like 0x0), the logic still works correctly
// because we check for None rather than comparing values
}
/// Transition to latency wait state
@ -584,10 +603,17 @@ impl Intel4001 {
/// Hardware: ROM needs 500ns to access data after address is latched
fn handle_latency_wait(&mut self) {
if let Some(latch_time) = self.address_latch_time {
if latch_time.elapsed() >= self.access_time {
let elapsed = latch_time.elapsed();
println!("DEBUG: {} - handle_latency_wait: elapsed={:?}, access_time={:?}, ready={}",
self.base.name(), elapsed, self.access_time, self.full_address_ready);
if elapsed >= self.access_time {
// Latency elapsed, transition to data driving
// Data will be driven on next Φ2 rising edge
println!("DEBUG: {} - Latency elapsed, transitioning to DriveData", self.base.name());
self.start_data_driving();
}
} else {
println!("DEBUG: {} - handle_latency_wait: no latch_time set", self.base.name());
}
}
@ -603,6 +629,9 @@ impl Intel4001 {
fn handle_data_driving(&mut self) {
let (sync, chip_select, io_select, _) = self.read_control_pins();
println!("DEBUG: {} - handle_data_driving: SYNC={}, CM={}, CI={}, Address_Ready={}",
self.base.name(), sync, chip_select, io_select, self.full_address_ready);
// Memory read: CM=1 (chip_select), CI=0 (!io_select), valid address
if sync && chip_select && !io_select && self.full_address_ready {
// All conditions met: drive data on bus
@ -610,20 +639,24 @@ impl Intel4001 {
let address = self.last_address;
if (address as usize) < self.memory.len() {
let data = self.memory[address as usize];
println!("DEBUG: {} - All conditions met, driving data 0x{:x} to address 0x{:x}", self.base.name(), data, address);
self.write_data_bus(data);
// Note: Don't call return_to_idle() here - wait for Φ2 falling edge
} else {
// Invalid address, tri-state
println!("DEBUG: {} - Invalid address 0x{:x}, tri-stating", self.base.name(), address);
self.tri_state_data_bus();
}
} else {
// Bus contention guard: ROM should not drive when conditions not met
// In real hardware, this would cause a short if CPU is still driving
if self.full_address_ready {
eprintln!("WARNING: {} - Bus contention detected! ROM attempting to drive data bus when conditions not met (SYNC={}, CM={}, CI={}, Address_Ready={})",
println!("DEBUG: {} - Bus contention detected! ROM attempting to drive data bus when conditions not met (SYNC={}, CM={}, CI={}, Address_Ready={})",
self.base.name(), sync, chip_select, io_select, self.full_address_ready);
}
// Conditions not met, tri-state
println!("DEBUG: {} - Conditions not met, tri-stating (SYNC={}, CM={}, CI={}, Address_Ready={})",
self.base.name(), sync, chip_select, io_select, self.full_address_ready);
self.tri_state_data_bus();
}
}
@ -754,6 +787,14 @@ impl Intel4001 {
pub fn get_input_latch(&self) -> u8 {
self.input_latch
}
/// Debug function to log state transitions for troubleshooting
/// Parameters: test_name - Name of the test for context
pub fn debug_state_transitions(&self, test_name: &str) {
println!("{} - State: {:?}, High: {:?}, Low: {:?}, Address: 0x{:x}, Ready: {}, Latch time: {:?}",
test_name, self.memory_state, self.address_high_nibble, self.address_low_nibble,
self.last_address, self.full_address_ready, self.address_latch_time);
}
}
// Custom formatter for debugging
@ -874,7 +915,16 @@ mod tests {
let d2_pin = rom.get_pin("D2").unwrap();
let d3_pin = rom.get_pin("D3").unwrap();
// Initialize clock pins to Low to ensure proper edge detection
{
let mut phi1_guard = phi1_pin.lock().unwrap();
let mut phi2_guard = phi2_pin.lock().unwrap();
phi1_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
phi2_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
}
// Set up memory read operation: SYNC=1, CM=1, CI=0 (memory access)
// These must remain set throughout the entire memory operation
{
let mut sync_guard = sync_pin.lock().unwrap();
let mut cm_guard = cm_pin.lock().unwrap();
@ -995,6 +1045,9 @@ mod tests {
let test_data = vec![0x12];
rom.load_rom_data(test_data, 0).unwrap();
// Initial state debug
rom.debug_state_transitions("INITIAL");
// Get pin references
let sync_pin = rom.get_pin("SYNC").unwrap();
let cm_pin = rom.get_pin("CM").unwrap();
@ -1034,26 +1087,34 @@ mod tests {
.unwrap()
.set_driver(Some("TEST".into()), PinValue::High);
rom.update(); // rising edge -> latch high nibble
rom.debug_state_transitions("AFTER_HIGH_NIBBLE_RISING");
phi1_pin
.lock()
.unwrap()
.set_driver(Some("TEST".into()), PinValue::Low);
rom.update(); // falling edge
println!(
"After Φ1 high - State: {:?}, High nibble: {:?}, Low nibble: {:?}",
rom.memory_state, rom.address_high_nibble, rom.address_low_nibble
);
rom.debug_state_transitions("AFTER_HIGH_NIBBLE_FALLING");
// Phase 2: Address phase - latch low nibble (0x0)
// Re-assert control pins to ensure they're maintained during entire operation
{
let mut sync_guard = sync_pin.lock().unwrap();
let mut cm_guard = cm_pin.lock().unwrap();
let mut ci_guard = ci_pin.lock().unwrap();
sync_guard.set_driver(Some("TEST".to_string()), PinValue::High);
cm_guard.set_driver(Some("TEST".to_string()), PinValue::High);
ci_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Memory access
}
// Tri-state data bus to let ROM take control
{
let mut d0_guard = d0_pin.lock().unwrap();
let mut d1_guard = d1_pin.lock().unwrap();
let mut d2_guard = d2_pin.lock().unwrap();
let mut d3_guard = d3_pin.lock().unwrap();
d0_guard.set_driver(Some("TEST".into()), PinValue::Low); // Bit 0 = 0
d1_guard.set_driver(Some("TEST".into()), PinValue::Low); // Bit 1 = 0
d2_guard.set_driver(Some("TEST".into()), PinValue::Low); // Bit 2 = 0
d3_guard.set_driver(Some("TEST".into()), PinValue::Low); // Bit 3 = 0
d0_guard.set_driver(Some("TEST".into()), PinValue::HighZ);
d1_guard.set_driver(Some("TEST".into()), PinValue::HighZ);
d2_guard.set_driver(Some("TEST".into()), PinValue::HighZ);
d3_guard.set_driver(Some("TEST".into()), PinValue::HighZ);
}
// --- Low nibble ---
@ -1062,32 +1123,98 @@ mod tests {
.unwrap()
.set_driver(Some("TEST".into()), PinValue::High);
rom.update(); // rising edge -> latch low nibble
rom.debug_state_transitions("AFTER_LOW_NIBBLE_RISING");
phi1_pin
.lock()
.unwrap()
.set_driver(Some("TEST".into()), PinValue::Low);
rom.update(); // falling edge
println!("After second Φ1 high - State: {:?}, High nibble: {:?}, Low nibble: {:?}, Address: 0x{:x}", rom.memory_state, rom.address_high_nibble, rom.address_low_nibble, rom.last_address);
rom.debug_state_transitions("AFTER_LOW_NIBBLE_FALLING");
// Advance simulated time to exceed access_time (1ns)
rom.debug_state_transitions("BEFORE_SLEEP");
std::thread::sleep(Duration::from_nanos(2));
rom.debug_state_transitions("AFTER_SLEEP");
// --- Data phase ---
// First set Φ2 to Low, then High to ensure proper edge detection
phi2_pin
.lock()
.unwrap()
.set_driver(Some("TEST".into()), PinValue::Low);
rom.update(); // ensure low state
phi2_pin
.lock()
.unwrap()
.set_driver(Some("TEST".into()), PinValue::High);
rom.update(); // rising edge -> drive data
rom.debug_state_transitions("AFTER_PHI2_RISING");
// Assert DriveData state while Φ2 is high
// After sleep, latency should have elapsed, so should transition to DriveData on Φ2 rising
// The state should transition to DriveData during the Φ2 rising edge
assert_eq!(rom.memory_state, MemoryState::DriveData);
println!("After Φ2 high - State: {:?}", rom.memory_state);
// Debug: Check what data the ROM thinks it should drive
let address = rom.last_address;
let expected_data = rom.memory[address as usize];
println!("DEBUG: ROM address 0x{:x}, data at address: 0x{:x}", address, expected_data);
// Debug: Check the bit extraction logic
let bit0 = (expected_data >> 0) & 1;
let bit1 = (expected_data >> 1) & 1;
let bit2 = (expected_data >> 2) & 1;
let bit3 = (expected_data >> 3) & 1;
println!("DEBUG: Bit extraction - bit0: {}, bit1: {}, bit2: {}, bit3: {}", bit0, bit1, bit2, bit3);
// Debug: Check actual pin states and settlement status
let d0_actual = d0_pin.lock().unwrap().read();
let d1_actual = d1_pin.lock().unwrap().read();
let d2_actual = d2_pin.lock().unwrap().read();
let d3_actual = d3_pin.lock().unwrap().read();
let d0_immediate = d0_pin.lock().unwrap().read_immediate();
let d1_immediate = d1_pin.lock().unwrap().read_immediate();
let d2_immediate = d2_pin.lock().unwrap().read_immediate();
let d3_immediate = d3_pin.lock().unwrap().read_immediate();
let d0_settled = d0_pin.lock().unwrap().is_settled();
let d1_settled = d1_pin.lock().unwrap().is_settled();
let d2_settled = d2_pin.lock().unwrap().is_settled();
let d3_settled = d3_pin.lock().unwrap().is_settled();
println!("DEBUG: D0 actual: {:?} (bit 0: {}), immediate: {:?}, settled: {}", d0_actual, bit0, d0_immediate, d0_settled);
println!("DEBUG: D1 actual: {:?} (bit 1: {}), immediate: {:?}, settled: {}", d1_actual, bit1, d1_immediate, d1_settled);
println!("DEBUG: D2 actual: {:?} (bit 2: {}), immediate: {:?}, settled: {}", d2_actual, bit2, d2_immediate, d2_settled);
println!("DEBUG: D3 actual: {:?} (bit 3: {}), immediate: {:?}, settled: {}", d3_actual, bit3, d3_immediate, d3_settled);
// Debug: Check actual pin states immediately after data driving
let d0_actual = d0_pin.lock().unwrap().read();
let d1_actual = d1_pin.lock().unwrap().read();
let d2_actual = d2_pin.lock().unwrap().read();
let d3_actual = d3_pin.lock().unwrap().read();
println!("DEBUG: After data driving - D0: {:?}, D1: {:?}, D2: {:?}, D3: {:?}", d0_actual, d1_actual, d2_actual, d3_actual);
// Debug: Check what the ROM thinks it should be driving
let expected_data = 0x12;
let bit0 = (expected_data >> 0) & 1;
let bit1 = (expected_data >> 1) & 1;
let bit2 = (expected_data >> 2) & 1;
let bit3 = (expected_data >> 3) & 1;
println!("DEBUG: Expected bits - bit0: {}, bit1: {}, bit2: {}, bit3: {}", bit0, bit1, bit2, bit3);
// Verify data is driven on bus while Φ2 is high: 0x12 = 0001 0010
// 0x12 = 18 decimal = 0001 0010 binary
// For 4-bit data bus: D3=0, D2=0, D1=1, D0=0
// Small delay to allow pin state to settle
std::thread::sleep(Duration::from_micros(1));
assert_eq!(d0_pin.lock().unwrap().read(), PinValue::Low); // Bit 0 = 0
assert_eq!(d1_pin.lock().unwrap().read(), PinValue::High); // Bit 1 = 1
assert_eq!(d2_pin.lock().unwrap().read(), PinValue::Low); // Bit 2 = 0
assert_eq!(d3_pin.lock().unwrap().read(), PinValue::High); // Bit 3 = 1
assert_eq!(d3_pin.lock().unwrap().read(), PinValue::Low); // Bit 3 = 0 (NOT 1!)
phi2_pin
.lock()
@ -1128,17 +1255,9 @@ mod tests {
ci_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Memory access
}
// Set address 0x0 on data bus
{
let mut d0_guard = d0_pin.lock().unwrap();
let mut d1_guard = d1_pin.lock().unwrap();
let mut d2_guard = d2_pin.lock().unwrap();
let mut d3_guard = d3_pin.lock().unwrap();
d0_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
d1_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
d2_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
d3_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
}
// Tri-state data bus to let ROM take control
// Note: Don't clear ROM's driver - let ROM set its own driver when it drives data
// The ROM uses driver name format "{}_DATA" (e.g., "ROM_4001_DATA")
// Set Φ1 high, Φ2 low - should start memory operation
phi1_pin
@ -1156,16 +1275,16 @@ mod tests {
// Should have transitioned to AddressPhase
assert_eq!(rom.memory_state, MemoryState::AddressPhase);
// Set address on data bus for latching
// Set address on data bus for latching (CPU drives during address phase)
{
let mut d0_guard = d0_pin.lock().unwrap();
let mut d1_guard = d1_pin.lock().unwrap();
let mut d2_guard = d2_pin.lock().unwrap();
let mut d3_guard = d3_pin.lock().unwrap();
d0_guard.set_driver(Some("TEST".into()), PinValue::Low);
d1_guard.set_driver(Some("TEST".into()), PinValue::Low);
d2_guard.set_driver(Some("TEST".into()), PinValue::Low);
d3_guard.set_driver(Some("TEST".into()), PinValue::Low);
d0_guard.set_driver(Some("CPU".to_string()), PinValue::Low);
d1_guard.set_driver(Some("CPU".to_string()), PinValue::Low);
d2_guard.set_driver(Some("CPU".to_string()), PinValue::Low);
d3_guard.set_driver(Some("CPU".to_string()), PinValue::Low);
}
// --- High nibble ---
@ -1201,10 +1320,12 @@ mod tests {
assert_eq!(rom.memory_state, MemoryState::DriveData);
// Verify data is driven on bus while Φ2 is high: 0x12 = 0001 0010
// 0x12 = 18 decimal = 0001 0010 binary
// For 4-bit data bus: D3=0, D2=0, D1=1, D0=0
assert_eq!(d0_pin.lock().unwrap().read(), PinValue::Low); // Bit 0 = 0
assert_eq!(d1_pin.lock().unwrap().read(), PinValue::High); // Bit 1 = 1
assert_eq!(d2_pin.lock().unwrap().read(), PinValue::Low); // Bit 2 = 0
assert_eq!(d3_pin.lock().unwrap().read(), PinValue::High); // Bit 3 = 1
assert_eq!(d3_pin.lock().unwrap().read(), PinValue::Low); // Bit 3 = 0 (NOT 1!)
phi2_pin
.lock()
@ -1246,16 +1367,16 @@ mod tests {
}
// Test complete cycle for address 0x00
// Step 1: Set address high nibble (0x0) on data bus
// Step 1: Clear CPU driver to let ROM take control
{
let mut d0_guard = d0_pin.lock().unwrap();
let mut d1_guard = d1_pin.lock().unwrap();
let mut d2_guard = d2_pin.lock().unwrap();
let mut d3_guard = d3_pin.lock().unwrap();
d0_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Bit 0 = 0
d1_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Bit 1 = 0
d2_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Bit 2 = 0
d3_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Bit 3 = 0
d0_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
d1_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
d2_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
d3_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
}
// Step 2: High nibble
@ -1270,16 +1391,16 @@ mod tests {
.set_driver(Some("TEST".into()), PinValue::High);
rom.update(); // rising edge for high nibble
// Step 3: Set address low nibble (0x0) on data bus
// Step 3: Clear CPU driver to let ROM take control
{
let mut d0_guard = d0_pin.lock().unwrap();
let mut d1_guard = d1_pin.lock().unwrap();
let mut d2_guard = d2_pin.lock().unwrap();
let mut d3_guard = d3_pin.lock().unwrap();
d0_guard.set_driver(Some("TEST".into()), PinValue::Low); // Bit 0 = 0
d1_guard.set_driver(Some("TEST".into()), PinValue::Low); // Bit 1 = 0
d2_guard.set_driver(Some("TEST".into()), PinValue::Low); // Bit 2 = 0
d3_guard.set_driver(Some("TEST".into()), PinValue::Low); // Bit 3 = 0
d0_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
d1_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
d2_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
d3_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
}
// Step 4: Low nibble
@ -1305,10 +1426,12 @@ mod tests {
rom.update(); // rising edge -> drive data
// Step 5: Verify data is driven on bus while Φ2 is high: 0x12 = 0001 0010
// 0x12 = 18 decimal = 0001 0010 binary
// For 4-bit data bus: D3=0, D2=0, D1=1, D0=0
assert_eq!(d0_pin.lock().unwrap().read(), PinValue::Low); // Bit 0 = 0
assert_eq!(d1_pin.lock().unwrap().read(), PinValue::High); // Bit 1 = 1
assert_eq!(d2_pin.lock().unwrap().read(), PinValue::Low); // Bit 2 = 0
assert_eq!(d3_pin.lock().unwrap().read(), PinValue::High); // Bit 3 = 1 (0x12 = 0001 0010)
assert_eq!(d3_pin.lock().unwrap().read(), PinValue::Low); // Bit 3 = 0 (NOT 1!)
phi2_pin
.lock()
@ -1320,16 +1443,16 @@ mod tests {
// Reset memory state first
rom.return_to_idle();
// Step 1: Set address high nibble (0x0) on data bus
// Step 1: Clear CPU driver to let ROM take control
{
let mut d0_guard = d0_pin.lock().unwrap();
let mut d1_guard = d1_pin.lock().unwrap();
let mut d2_guard = d2_pin.lock().unwrap();
let mut d3_guard = d3_pin.lock().unwrap();
d0_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Bit 0 = 0
d1_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Bit 1 = 0
d2_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Bit 2 = 0
d3_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Bit 3 = 0
d0_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
d1_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
d2_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
d3_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
}
// Step 2: High nibble
@ -1344,16 +1467,16 @@ mod tests {
.set_driver(Some("TEST".into()), PinValue::High);
rom.update(); // rising edge for high nibble
// Step 3: Set address low nibble (0x1) on data bus
// Step 3: Clear CPU driver to let ROM take control
{
let mut d0_guard = d0_pin.lock().unwrap();
let mut d1_guard = d1_pin.lock().unwrap();
let mut d2_guard = d2_pin.lock().unwrap();
let mut d3_guard = d3_pin.lock().unwrap();
d0_guard.set_driver(Some("TEST".into()), PinValue::High); // Bit 0 = 1
d1_guard.set_driver(Some("TEST".into()), PinValue::Low); // Bit 1 = 0
d2_guard.set_driver(Some("TEST".into()), PinValue::Low); // Bit 2 = 0
d3_guard.set_driver(Some("TEST".into()), PinValue::Low); // Bit 3 = 0
d0_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
d1_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
d2_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
d3_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
}
// Step 4: Low nibble
@ -1379,10 +1502,12 @@ mod tests {
rom.update(); // rising edge -> drive data
// Step 5: Verify data is driven on bus while Φ2 is high: 0x34 = 0011 0100
// 0x34 = 52 decimal = 0011 0100 binary
// For 4-bit data bus: D3=0, D2=0, D1=1, D0=1
assert_eq!(d0_pin.lock().unwrap().read(), PinValue::Low); // Bit 0 = 0
assert_eq!(d1_pin.lock().unwrap().read(), PinValue::Low); // Bit 1 = 0
assert_eq!(d2_pin.lock().unwrap().read(), PinValue::High); // Bit 2 = 1
assert_eq!(d3_pin.lock().unwrap().read(), PinValue::High); // Bit 3 = 1 (0x34 = 0011 0100)
assert_eq!(d3_pin.lock().unwrap().read(), PinValue::Low); // Bit 3 = 0 (NOT 1!)
phi2_pin
.lock()
@ -1571,10 +1696,10 @@ mod tests {
let mut d1_guard = d1_pin.lock().unwrap();
let mut d2_guard = d2_pin.lock().unwrap();
let mut d3_guard = d3_pin.lock().unwrap();
d0_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Bit 0 = 0
d1_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Bit 1 = 0
d2_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Bit 2 = 0
d3_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Bit 3 = 0
d0_guard.set_driver(Some("TEST".to_string()), PinValue::HighZ);
d1_guard.set_driver(Some("TEST".to_string()), PinValue::HighZ);
d2_guard.set_driver(Some("TEST".to_string()), PinValue::HighZ);
d3_guard.set_driver(Some("TEST".to_string()), PinValue::HighZ);
}
// High nibble
@ -1595,10 +1720,10 @@ mod tests {
let mut d1_guard = d1_pin.lock().unwrap();
let mut d2_guard = d2_pin.lock().unwrap();
let mut d3_guard = d3_pin.lock().unwrap();
d0_guard.set_driver(Some("TEST".into()), PinValue::Low); // Bit 0 = 0
d1_guard.set_driver(Some("TEST".into()), PinValue::Low); // Bit 1 = 0
d2_guard.set_driver(Some("TEST".into()), PinValue::Low); // Bit 2 = 0
d3_guard.set_driver(Some("TEST".into()), PinValue::Low); // Bit 3 = 0
d0_guard.set_driver(Some("TEST".into()), PinValue::HighZ);
d1_guard.set_driver(Some("TEST".into()), PinValue::HighZ);
d2_guard.set_driver(Some("TEST".into()), PinValue::HighZ);
d3_guard.set_driver(Some("TEST".into()), PinValue::HighZ);
}
// Low nibble
@ -1624,10 +1749,12 @@ mod tests {
rom.update(); // rising edge -> drive data
// Should have data 0x12 on bus while Φ2 is high: 0001 0010
// 0x12 = 18 decimal = 0001 0010 binary
// For 4-bit data bus: D3=0, D2=0, D1=1, D0=0
assert_eq!(d0_pin.lock().unwrap().read(), PinValue::Low); // Bit 0 = 0
assert_eq!(d1_pin.lock().unwrap().read(), PinValue::High); // Bit 1 = 1
assert_eq!(d2_pin.lock().unwrap().read(), PinValue::Low); // Bit 2 = 0
assert_eq!(d3_pin.lock().unwrap().read(), PinValue::High); // Bit 3 = 1
assert_eq!(d3_pin.lock().unwrap().read(), PinValue::Low); // Bit 3 = 0 (NOT 1!)
phi2_pin
.lock()
@ -1638,16 +1765,16 @@ mod tests {
// Cycle 3: Next memory operation for address 0x01
rom.return_to_idle();
// Set address high nibble (0x0) for address 0x01
// Clear CPU driver to let ROM take control for address 0x01
{
let mut d0_guard = d0_pin.lock().unwrap();
let mut d1_guard = d1_pin.lock().unwrap();
let mut d2_guard = d2_pin.lock().unwrap();
let mut d3_guard = d3_pin.lock().unwrap();
d0_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Bit 0 = 0
d1_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Bit 1 = 0
d2_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Bit 2 = 0
d3_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Bit 3 = 0
d0_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
d1_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
d2_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
d3_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
}
// High nibble
@ -1662,16 +1789,16 @@ mod tests {
.set_driver(Some("TEST".into()), PinValue::High);
rom.update(); // rising edge for high nibble
// Set address low nibble (0x1) for address 0x01
// Clear CPU driver to let ROM take control for low nibble
{
let mut d0_guard = d0_pin.lock().unwrap();
let mut d1_guard = d1_pin.lock().unwrap();
let mut d2_guard = d2_pin.lock().unwrap();
let mut d3_guard = d3_pin.lock().unwrap();
d0_guard.set_driver(Some("TEST".into()), PinValue::High); // Bit 0 = 1
d1_guard.set_driver(Some("TEST".into()), PinValue::Low); // Bit 1 = 0
d2_guard.set_driver(Some("TEST".into()), PinValue::Low); // Bit 2 = 0
d3_guard.set_driver(Some("TEST".into()), PinValue::Low); // Bit 3 = 0
d0_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
d1_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
d2_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
d3_guard.set_driver(Some("CPU".to_string()), PinValue::HighZ);
}
// Low nibble
@ -1697,10 +1824,12 @@ mod tests {
rom.update(); // rising edge -> drive data
// Should have data 0x34 on bus while Φ2 is high: 0011 0100
// 0x34 = 52 decimal = 0011 0100 binary
// For 4-bit data bus: D3=0, D2=0, D1=1, D0=1
assert_eq!(d0_pin.lock().unwrap().read(), PinValue::Low); // Bit 0 = 0
assert_eq!(d1_pin.lock().unwrap().read(), PinValue::Low); // Bit 1 = 0
assert_eq!(d2_pin.lock().unwrap().read(), PinValue::High); // Bit 2 = 1
assert_eq!(d3_pin.lock().unwrap().read(), PinValue::High); // Bit 3 = 1
assert_eq!(d3_pin.lock().unwrap().read(), PinValue::Low); // Bit 3 = 0 (NOT 1!)
phi2_pin
.lock()

1265
src/components/memory/intel_4002.rs
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File diff suppressed because it is too large Load diff

1
src/components/memory/mod.rs
View file

@ -2,3 +2,4 @@ mod generic_ram;
pub mod generic_rom;
pub mod intel_4001;
pub mod intel_4002;
pub mod intel_4003;