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3
Cargo.lock generated
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@ -1,6 +1,6 @@
# This file is automatically @generated by Cargo.
# It is not intended for manual editing.
version = 4
version = 3
[[package]]
name = "ab_glyph"
@ -2503,7 +2503,6 @@ dependencies = [
"eframe",
"egui",
"gtk",
"parking_lot",
"ratatui",
"raw-window-handle 0.5.2",
"rfd",

1
Cargo.toml
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@ -17,7 +17,6 @@ egui = "0.24"
eframe = { version = "0.24", default-features = false, features = ["default_fonts", "glow", "persistence"] }
rfd = "0.14"
raw-window-handle = "0.5"
parking_lot = "0.12"
# Force compatible versions for Rust 1.81.0
[dependencies.tokio]

55
README.md
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@ -26,7 +26,7 @@ Intel 4004 CPU (4-bit microprocessor)
├── ALU with carry/borrow logic
├── Program counter and stack
├── Two-phase clock interface
└── Unified state machine (FetchByte1, FetchByte2, Execute states)
└── Unified state machine (FetchInstruction, ExecuteInstruction states)
Intel 4001 ROM (256 bytes with I/O)
├── Mask-programmable ROM storage
@ -123,48 +123,36 @@ For more detailed information about the unified state machine implementation, se
rusty_emu/
├── src/ # Source code
│ ├── lib.rs # Library exports
│ ├── main.rs # Binary entry point with GUI, console, and JSON configuration
│ ├── main.rs # Binary entry point with JSON configuration
│ ├── component.rs # Core component traits
│ ├── connection.rs # Component interconnection system
│ ├── pin.rs # Pin and signal system
│ ├── types.rs # Common type definitions
│ ├── system_config.rs # JSON-based system configuration system
│ ├── gui/ # Graphical user interface module
│ ├── console.rs # Interactive console interface
│ ├── gui.rs # Graphical user interface module
│ │ ├── components.rs # GUI component implementations
│ │ ├── state.rs # GUI state management
│ │ └── mod.rs # GUI module exports
│ └── components/ # Hardware components
│ ├── common/ # Shared Intel 400x functionality
│ ├── cpu/ # CPU implementations (Intel 4004, MOS 6502, WDC 65C02)
│ ├── memory/ # Memory components (Intel 4001, 4002, 4003)
│ └── clock/ # Clock generation
│ ├── components/ # Hardware components
│ │ ├── common/ # Shared Intel 400x functionality
│ │ ├── cpu/ # CPU implementations
│ │ ├── memory/ # Memory components
│ │ └── clock/ # Clock generation
│ └── systems/ # System integration (legacy)
├── configs/ # JSON system configuration files
│ ├── mcs4_basic.json # Basic MCS-4 system configuration
│ ├── mcs4_max.json # Fig.1 MCS-4 Max system configuration
│ ├── mcs4_io_demo.json # I/O demonstration configuration
│ └── console_config.xml # Console interface configuration
│ └── mcs4_max.json # Fig.1 MCS-4 Max system configuration
├── programs/ # Binary program files
│ ├── README.md # Program documentation
│ ├── fibonacci.bin # Example Fibonacci program
│ └── fibonacci_output.bin # Fibonacci with output port visibility
│ └── fibonacci.bin # Example Fibonacci program
├── tests/ # Comprehensive test suite
│ ├── README.md # Test documentation
│ ├── lib.rs # Test library
│ ├── mocks.rs # Mock implementations
│ ├── intel_400x_tests.rs # Common functionality tests
│ ├── intel_4001_state_machine_test.rs # 4001 state machine tests
│ ├── intel_4002_state_machine_test.rs # 4002 state machine tests
│ ├── intel_4003_state_machine_test.rs # 4003 state machine tests
│ ├── intel_4004_state_machine_test.rs # 4004 state machine tests
│ ├── integration_tests.rs # System integration tests
│ ├── json_integration_tests.rs # JSON config tests
│ ├── simple_test.rs # Core functionality demo
│ ├── gui_tests.rs # GUI component tests
│ └── gui_integration_tests.rs # GUI integration tests
├── plans/ # Design documents
│ ├── intel_4004_opcode_fix.md # Opcode fix design document
│ ├── codebase_analysis.md # Codebase analysis
│ └── system_control_architecture.md # System architecture
└── CONSOLE_README.md # Console interface documentation
│ ├── mock_based_tests.rs # Mock-based tests
│ ├── property_based_tests.rs # Property verification
│ └── integration_tests.rs # System integration tests
└── docs/ # Documentation
```
## Quick Start
@ -585,13 +573,7 @@ The test suite demonstrates:
- Core component architecture with trait-based design
- Intel 4001 ROM implementation with I/O ports
- **Intel 4004 CPU with complete instruction set (all 46 instructions)**
- **Correct opcode decoding table per Intel 4004 datasheet**
- **Two-byte instruction handling (FetchByte1→FetchByte2→Execute state machine)**
- **I/O and RAM instructions fully implemented (WRM, WMP, WRR, WPM, WR0-WR3, SBM, RDM, RDR, ADM, RD0-RD3)**
- **Accumulator group instructions (CLB, CLC, IAC, CMC, CMA, RAL, RAR, TCC, TCS, STC, DAA, KBP, DCL)**
- **JCN condition decoding with correct bit-field (invert/ACC zero/carry/TEST pin)**
- **SRC properly implemented using register pairs with src_address storage**
- Intel 4004 CPU structure and instruction framework
- Intel 4002 RAM implementation with refresh circuitry
- Intel 4003 Shift Register implementation
- **Unified state machine architecture for all Intel 400x components**
@ -606,6 +588,7 @@ The test suite demonstrates:
### 🚧 In Progress
- Complete Intel 4004 instruction execution engine
- System integration and timing verification
- Performance optimization and benchmarking

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@ -1,296 +0,0 @@
# Observer Pattern and UI Layout Configuration Implementation Plan
## Overview
This plan implements two key improvements to the rusty_emu project:
1. **Observer Pattern**: Replace inefficient polling with event-driven state updates
2. **UI Layout Configuration**: Enable configurable GUI layouts from JSON config files
## Current Issues
### Performance Issues
- Console polls system state at 100ms intervals (inefficient)
- GUI uses `try_lock()` but still has potential contention
- No way to configure GUI layout from JSON config
### Architecture Limitations
- Tight coupling between components and UI
- No standardized way to notify UI of state changes
- Hardcoded UI layouts
## Solution Architecture
### Observer Pattern Implementation
```mermaid
graph TD
A[SystemObserver Trait] --> B[CPU Observer]
A --> C[RAM Observer]
A --> D[ROM Observer]
B --> E[ConfigurableSystem]
C --> E
D --> E
E --> F[Console UI]
E --> G[GUI Interface]
F --> H[Event-driven Updates]
G --> H
```
### UI Layout Configuration
```mermaid
graph LR
A[SystemConfig JSON] --> B[UI Layout Section]
B --> C[Component Positions]
B --> D[Component Sizes]
B --> E[Display Options]
C --> F[GUI Renderer]
D --> F
E --> F
```
## Implementation Details
### 1. SystemObserver Trait (Fine-grained with Filtering)
```rust
#[derive(Debug, Clone)]
pub enum ObserverFilter {
All,
CpuOnly,
MemoryOnly,
StateChangesOnly,
RegisterChangesOnly,
}
pub trait SystemObserver: Send + Sync {
fn get_filter(&self) -> ObserverFilter { return ObserverFilter::All; }
fn on_state_change(&self, component: &str, old_state: ComponentState, new_state: ComponentState);
fn on_ram_change(&self, chip: &str, bank: usize, address: u8, old_value: u8, new_value: u8);
fn on_rom_change(&self, chip: &str, address: u16, old_value: u8, new_value: u8);
fn on_cpu_register_change(&self, cpu: &str, register: &str, old_value: u8, new_value: u8);
fn on_cpu_pc_change(&self, cpu: &str, old_pc: u16, new_pc: u16);
fn on_cpu_instruction_executed(&self, cpu: &str, instruction: u8, pc: u16);
}
```
### 2. Enhanced SystemConfig
```rust
#[derive(Debug, Clone, Serialize, Deserialize)]
pub struct SystemConfig {
pub name: String,
pub description: String,
pub version: String,
pub metadata: HashMap<String, serde_json::Value>,
pub components: HashMap<String, ComponentConfig>,
pub connections: HashMap<String, ConnectionConfig>,
pub layout: Option<LayoutConfig>,
// NEW: UI Layout configuration
pub ui_layout: Option<UiLayoutConfig>,
}
#[derive(Debug, Clone, Serialize, Deserialize)]
pub struct UiLayoutConfig {
pub console: Option<ConsoleLayoutConfig>,
pub gui: Option<GuiLayoutConfig>,
}
#[derive(Debug, Clone, Serialize, Deserialize)]
pub struct GuiLayoutConfig {
pub components: HashMap<String, ComponentLayoutConfig>,
pub grid_size: Option<[usize; 2]>,
pub refresh_rate_ms: Option<u64>,
}
#[derive(Debug, Clone, Serialize, Deserialize)]
pub struct ComponentLayoutConfig {
pub position: [usize; 2],
pub size: [usize; 2],
pub visible: Option<bool>,
pub display_format: Option<String>,
}
```
### 3. Observer Registration in ConfigurableSystem
```rust
pub struct ConfigurableSystem {
config: SystemConfig,
components: HashMap<String, Arc<Mutex<Box<dyn Component>>>>,
is_running: Arc<Mutex<bool>>,
component_handles: Arc<Mutex<Option<ComponentHandles>>>,
// NEW: Observer registry
observers: Arc<Mutex<Vec<Box<dyn SystemObserver>>>>,
}
```
### 4. Component Integration
Each component will notify observers of state changes:
- **Intel4004 CPU**: Register changes, PC changes, instruction execution
- **Intel4001 ROM**: Memory reads, address changes
- **Intel4002 RAM**: Memory reads/writes, I/O changes
### 5. UI Updates
#### Console Updates (Performance Target: 50% CPU reduction, sub-10ms responsiveness)
- Replace 100ms polling with event-driven updates using observer pattern
- Observer receives notifications and updates display immediately
- Implement filtering to reduce unnecessary UI updates
- Target: Reduce CPU usage by 50% compared to current polling
- Target: Update responsiveness to under 10ms for state changes
#### GUI Updates
- Use layout configuration from JSON for component positioning/sizing
- Position components according to config (basic implementation)
- Show/hide components based on config visibility settings
- Use observer pattern for real-time updates
- Support configurable refresh rates from UI layout config
## Configuration Examples
### Enhanced JSON Config
```json
{
"name": "IntelMcs4",
"description": "Basic MCS-4 System with CPU, Clock, 2 ROMs, and 1 RAM",
"version": "1.0",
"metadata": {
"author": "RustyEmu",
"created": "2024-01-01",
"cpu_speed": 750000,
"architecture": "mcs4",
"rom_count": 2,
"ram_count": 1
},
"components": {
"CPU_4004": {
"single": {
"component_type": "intel_4004",
"name": "CPU_4004",
"properties": {
"clock_speed": 750000
}
}
}
// ... other components
},
"connections": {
// ... existing connections
},
"layout": {
"grid_size": [10, 10],
"positions": {
"cpu": [1, 1],
"clock": [0, 0],
"rom1": [2, 0],
"rom2": [3, 0],
"ram": [2, 2]
}
},
"ui_layout": {
"console": {
"refresh_rate_ms": 50,
"show_ram": true,
"show_registers": true,
"show_system_info": true
},
"gui": {
"grid_size": [20, 20],
"components": {
"CPU_4004": {
"position": [1, 1],
"size": [20, 10],
"visible": true,
"display_format": "hex"
},
"RAM_4002": {
"position": [3, 2],
"size": [25, 15],
"visible": true,
"display_format": "hex"
},
"ROM_4001_1": {
"position": [2, 0],
"size": [20, 8],
"visible": true,
"display_format": "hex"
}
},
"refresh_rate_ms": 60
}
}
}
```
## Benefits
### Performance Improvements
- **Reduced CPU usage**: Event-driven vs polling
- **Better responsiveness**: Immediate updates vs 100ms delays
- **Less contention**: Observer pattern reduces lock contention
### User Experience
- **Configurable layouts**: Users can customize UI arrangement
- **Persistent settings**: Layouts saved in config files
- **Flexible display options**: Show/hide components, change formats
### Architecture Benefits
- **Loose coupling**: Components don't depend on UI
- **Extensibility**: Easy to add new observers
- **Maintainability**: Clear separation of concerns
## Implementation Steps
1. **Add SystemObserver trait** to `system_config.rs`
2. **Extend SystemConfig** with UI layout configuration
3. **Add observer registration** to `ConfigurableSystem`
4. **Implement observer notifications** in Intel4004 CPU
5. **Implement observer notifications** in Intel4001 ROM
6. **Implement observer notifications** in Intel4002 RAM
7. **Update console.rs** to use observer pattern
8. **Update GUI** to use observer pattern and layout configuration
9. **Add UI layout configuration** to existing JSON configs
10. **Test** the observer pattern and UI layout system
11. **Update documentation** with new features
## Testing Strategy
### Unit Tests
- Test observer registration and notification
- Test UI layout configuration parsing
- Test component state change notifications
### Integration Tests
- Test console with observer pattern
- Test GUI with layout configuration
- Test end-to-end state change propagation
### Performance Tests
- Measure CPU usage reduction
- Test responsiveness improvements
- Validate lock contention reduction
## Backward Compatibility
- Existing configs without `ui_layout` section will use defaults (console: 100ms, current GUI layout)
- Observer pattern is additive - doesn't break existing code, components work without observers
- ConfigurableSystem will handle missing `ui_layout` gracefully with sensible defaults
- Gradual migration path: existing configs continue to work, new configs get enhanced features
- No breaking changes to existing JSON configs - only additive new section
## Future Enhancements
- **Multiple observer types**: Different observers for different concerns
- **Layout templates**: Predefined layouts for different use cases
- **Dynamic layout editing**: Runtime layout modification
- **Observer filtering**: Selective notification based on component types

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@ -1,218 +0,0 @@
# System Control Architecture Design
## Overview
This document outlines the architecture for implementing enhanced system start/stop/pause controls for the Intel MCS-4 emulator. The design provides centralized system management with fine-grained control over execution state and clock parameters.
## System Architecture
```mermaid
graph TB
subgraph "System Controller Layer"
SC[SystemController Trait]
EC[ExecutionController]
SS[SystemState Enum]
end
subgraph "System Layer"
CS[ConfigurableSystem]
SF[SystemFactory]
end
subgraph "Component Layer"
CPU[Intel4004]
CLK1[GenericClock]
CLK2[TwoPhaseClock]
ROM[Intel4001]
RAM[Intel4002]
end
subgraph "Interface Layer"
GUI[GUI Control Panel]
CON[Console Commands]
KB[Keyboard Shortcuts]
end
SC --> EC
EC --> CS
CS --> CPU
CS --> CLK1
CS --> CLK2
CS --> ROM
CS --> RAM
GUI --> SC
CON --> SC
KB --> SC
```
## Core Components
### 1. SystemController Trait
Defines the interface for system-wide control operations:
```rust
pub trait SystemController {
fn start(&mut self) -> Result<(), String>;
fn stop(&mut self) -> Result<(), String>;
fn pause(&mut self) -> Result<(), String>;
fn resume(&mut self) -> Result<(), String>;
fn is_running(&self) -> bool;
fn is_paused(&self) -> bool;
fn set_clock_frequency(&mut self, frequency: f64) -> Result<(), String>;
fn set_clock_enabled(&mut self, enabled: bool) -> Result<(), String>;
fn get_system_state(&self) -> SystemState;
fn get_clock_frequency(&self) -> f64;
fn get_clock_enabled(&self) -> bool;
}
```
### 2. SystemState Enum
Tracks the overall system execution state:
```rust
#[derive(Debug, Clone, Copy, PartialEq)]
pub enum SystemState {
Stopped,
Running,
Paused,
Error(String),
}
```
### 3. ExecutionController
Manages system lifecycle and coordinates component states:
```rust
pub struct ExecutionController {
system_state: SystemState,
clock_frequency: f64,
clock_enabled: bool,
components: HashMap<String, Arc<Mutex<Box<dyn Component>>>>,
}
```
## Component Enhancements
### Clock Components
**GenericClock & TwoPhaseClock Enhancements:**
- Add `paused` boolean field
- Implement `pause()` and `resume()` methods
- Add dynamic frequency adjustment with `set_frequency(f64)`
- Add `enable()` and `disable()` methods for power control
- Update `update()` methods to respect pause state
### CPU Component
**Intel4004 Enhancements:**
- Add `paused` boolean field
- Implement `pause()` to halt instruction execution
- Implement `resume()` to continue instruction execution
- Update `update()` to check pause state before executing instructions
- Maintain clock edge detection during pause for seamless resume
### Memory Components
**Intel4001 & Intel4002 Enhancements:**
- Add `paused` boolean field
- Implement `pause()` and `resume()` methods
- Update `update()` to respect pause state
- Ensure memory operations complete current cycle before pausing
## Interface Updates
### Console Commands
New console commands:
- `pause` / `p` - Pause system execution
- `resume` - Resume system execution
- `clock <freq>` - Set clock frequency (e.g., `clock 500000`)
- `clock on` / `clock off` - Enable/disable clock
- `speed +` / `speed -` - Increase/decrease clock frequency by 50%
### GUI Controls
New GUI control panel:
- System state indicator (Stopped/Running/Paused)
- Start/Stop/Pause/Resume buttons
- Clock frequency slider (100Hz - 10MHz range)
- Clock enable/disable toggle
- Real-time frequency display
- Keyboard shortcuts (Space=pause/resume, +/- for frequency)
## Configuration Schema
Extended JSON configuration with clock control:
```json
{
"clock_control": {
"initial_frequency": 750000,
"min_frequency": 1000,
"max_frequency": 10000000,
"frequency_step": 50000,
"auto_start": true
}
}
```
## Implementation Strategy
### Phase 1: Core Infrastructure
1. Implement SystemController trait
2. Create SystemState enum
3. Build ExecutionController
4. Update ConfigurableSystem
### Phase 2: Component Updates
1. Update clock components with pause/resume
2. Update CPU with execution control
3. Update memory components
4. Add dynamic frequency adjustment
### Phase 3: Interface Integration
1. Update console with new commands
2. Enhance GUI with control panel
3. Add keyboard shortcuts
4. Update configuration handling
### Phase 4: Testing & Documentation
1. Create comprehensive test suite
2. Update all documentation
3. Verify backwards compatibility
## Key Design Decisions
### Pause Behavior
- Complete system freeze including clock signals
- Components maintain state for seamless resume
- Clock edges are tracked but not propagated during pause
### Frequency Adjustment
- Dynamic adjustment during runtime
- Smooth transitions without glitches
- Validation against component limits
### State Management
- Centralized state tracking
- Thread-safe state updates
- Consistent state across all components
## Benefits
1. **Enhanced Control**: Fine-grained system management
2. **Dynamic Adjustment**: Runtime frequency changes
3. **Better Debugging**: Pause/resume for analysis
4. **User Experience**: Intuitive controls in both interfaces
5. **Extensibility**: Clean architecture for future enhancements
## Compatibility
- Maintains existing Component trait
- Backwards compatible with current configurations
- No breaking changes to existing APIs
- Optional features with sensible defaults

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@ -5,18 +5,18 @@ This directory contains binary program files for the Intel MCS-4 emulator.
## Available Programs
### fibonacci.bin
- **Size:** 17 bytes
- **Description:** Fibonacci sequence generator (stores results in RAM)
- **Algorithm:** Calculates first 8 Fibonacci numbers using registers R0-R3 and RAM
- **Instructions Used:** FIM, CLB, LD, ADD, WRM, XCH, ISZ, NOP
- **Output:** Results stored in RAM via WRM
- **Size:** 33 bytes (16 instructions × 2 bytes each + 1 extra byte)
- **Description:** Basic Fibonacci sequence generator (stores results in RAM)
- **Algorithm:** Calculates first 8 Fibonacci numbers using registers and RAM
- **Instructions Used:** LDM, LD, WRM, IAC, ADD, JCN, NOP
- **Output:** Results stored in RAM locations 0-7 (not visible to user)
### fibonacci_output.bin ✨ **RECOMMENDED**
- **Size:** 23 bytes
- **Size:** 55 bytes (27 instructions × 2 bytes each + 1 extra byte)
- **Description:** Enhanced Fibonacci sequence generator with output port visibility
- **Algorithm:** Calculates first 8 Fibonacci numbers and outputs them to RAM + output ports
- **Instructions Used:** FIM, CLB, LD, ADD, WRM, WMP, XCH, SRC, ISZ, NOP
- **Output:** Each Fibonacci number visible on output ports during execution
- **Algorithm:** Calculates first 8 Fibonacci numbers and outputs them to output ports
- **Instructions Used:** LDM, LD, WRM, IAC, ADD, JCN, NOP, SRC
- **Output:** Each Fibonacci number visible on output ports 0-7 during execution
- **Features:** Real-time visibility of calculation progress
### io_demo.bin ✨ **NEW**
@ -67,16 +67,14 @@ MCS-4 programs are stored as raw binary data where each instruction is represent
## Program Development Tips
### Making Programs Visible
- **Use Output Ports:** Write results to output ports via `WRR` (ROM port) or `WMP` (RAM port) for visibility
- **SRC Instruction:** Select target chip/address with `SRC` before I/O operations
- **Use Output Ports:** Write results to output ports (0x14-0x17) for visibility
- **SRC Instruction:** Select output port with `SRC` before `WRM`
- **Real-time Output:** Numbers appear on output ports during execution
- **System Monitoring:** Watch RAM contents and output port states in real-time
### Example Output Port Usage
```asm
FIM R0, 0x05 ; Load register pair R0/R1 with address (R0=0, R1=5)
SRC R0 ; Send register control from R0/R1 — selects chip/port
WRM ; Write ACC to RAM main memory at selected address
```
> **Note**: `SRC` takes a register *pair* number (0-7), not a direct port number. The register pair contents form the 8-bit address used for I/O and RAM operations. See the Intel 4004 datasheet for details.
LDM 5 ; Load value 5
SRC 0 ; Select output port 0
WRM ; Write to output port 0 (now visible to user)
```

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@ -8,35 +8,23 @@ written in Rust.
```
src/
├── lib.rs # Library root and main exports
├── main.rs # Binary entry point (GUI, console, CLI)
├── main.rs # Binary entry point
├── component.rs # Core component trait definitions
├── connection.rs # Component interconnection
├── pin.rs # Pin and signal abstractions
├── types.rs # Common type definitions (U12 address type)
├── system_config.rs # JSON-based system configuration
├── gui/ # Graphical user interface
│ ├── mod.rs # GUI module exports
│ ├── components.rs # GUI component implementations
│ └── state.rs # GUI state management
└── components/ # Hardware component implementations
├── mod.rs # Component module exports
├── common/ # Shared Intel 400x functionality
│ ├── mod.rs # Common exports
│ └── intel_400x.rs # Intel 400x unified state machine and traits
├── cpu/ # CPU implementations
│ ├── mod.rs # CPU module exports
│ ├── intel_4004.rs # Intel 4004 CPU (complete instruction set)
│ ├── mos_6502.rs # MOS 6502 CPU (placeholder)
│ └── wdc_65c02.rs # WDC 65C02 CPU (placeholder)
├── memory/ # Memory component implementations
│ ├── mod.rs # Memory module exports
│ ├── intel_4001.rs # Intel 4001 ROM with I/O ports
│ ├── intel_4002.rs # Intel 4002 RAM with output ports
│ └── intel_4003.rs # Intel 4003 shift register
└── clock/ # Clock generation components
├── mod.rs # Clock module exports
├── generic_clock.rs # Generic clock generator
└── two_phase_clock.rs # Two-phase clock for Intel 400x
├── connection.rs # Component interconnection
├── bus.rs # Data bus implementations
├── types.rs # Common type definitions
├── components/ # Hardware component implementations
│ ├── mod.rs # Component module exports
│ ├── common/ # Shared functionality
│ │ ├── mod.rs # Common exports
│ │ └── intel_400x.rs # Intel 400x common traits
│ ├── cpu/ # CPU implementations
│ ├── memory/ # Memory component implementations
│ └── clock/ # Clock generation components
└── systems/ # Complete system integrations
├── mod.rs # System module exports
└── intel_mcs_4.rs # Intel MCS-4 system
```
## Core Abstractions
@ -83,6 +71,8 @@ The system uses a two-phase clock architecture (Φ1, Φ2) that matches the Intel
- **Intel4001**: 256-byte ROM with 4-bit I/O ports
- **Intel4002**: 320-bit RAM with 4-bit output ports
- **Intel4003**: 10-bit shift register
- **GenericRAM**: Generic RAM implementation
- **GenericROM**: Generic ROM implementation
### Common Functionality (`src/components/common/`)
@ -98,18 +88,18 @@ The system uses a two-phase clock architecture (Φ1, Φ2) that matches the Intel
- **GenericClock**: Configurable clock generator
## System Configuration (`src/system_config.rs`)
## System Integration (`src/systems/`)
### JSON-Based System Configuration
### Intel MCS-4 System
Complete system configuration via JSON files featuring:
Complete Intel MCS-4 (Micro Computer System) implementation featuring:
- Intel 4004 CPU with configurable clock speed
- Intel 4001 ROM units with programmable contents
- Intel 4002 RAM units with bank selection
- Intel 4003 shift registers for I/O expansion
- System clock and timing configuration
- Automatic component interconnection via pin wiring
- Intel 4004 CPU
- Intel 4001 ROM units
- Intel 4002 RAM units
- Intel 4003 shift registers
- System clock and timing
- Component interconnection
## Key Features
@ -155,15 +145,17 @@ rom.update(); // Process one clock cycle
### System Integration
```rust
use rusty_emu::system_config::SystemFactory;
use rusty_emu::systems::intel_mcs_4::IntelMCS4;
// Create system from JSON configuration
let factory = SystemFactory::new();
let system = factory.create_from_json("configs/mcs4_basic.json") ?;
// Create complete MCS-4 system
let system = IntelMCS4::new();
// Load program into ROM
system.load_program(0, & program_data) ?;
// Get system information
let info = system.get_system_info();
println!("Created system: {} with {} components", info.name, info.component_count);
println!("Loaded system: {} with {} components", info.name, info.component_count);
// Run simulation (in a real application)
// system.run();

85
src/component.rs
View file

@ -1,16 +1,13 @@
use parking_lot::Mutex;
use std::any::Any;
use std::collections::HashMap;
use std::sync::{
atomic::{AtomicBool, Ordering},
Arc,
Arc, Mutex,
};
use std::thread;
use std::time::Duration;
use crate::component_timing::ComponentTiming;
use crate::pin::Pin;
use crate::virtual_clock::VirtualClock;
/// Core trait for all hardware components in the emulator
/// Provides the fundamental interface that all components must implement
@ -45,81 +42,10 @@ pub trait Component: Send + Sync {
/// Returns: true if component is running, false otherwise
fn is_running(&self) -> bool;
/// Set the component's running state
/// This is used by the system controller to manage component lifecycle
/// without requiring the blocking run() method
/// Parameters: running - New running state
fn set_running(&mut self, running: bool);
/// Get a reference to this component as Any for downcasting
/// This allows runtime type inspection to access component-specific methods
/// Returns: A reference to self as &dyn Any
fn as_any(&self) -> &dyn Any;
/// Get a mutable reference to this component as Any for downcasting
/// This allows runtime type inspection to access component-specific methods mutably
/// Returns: A mutable reference to self as &mut dyn Any
fn as_any_mut(&mut self) -> &mut dyn Any;
/// Update the component state for one simulation cycle at a specific virtual time.
///
/// This is the virtual-time-aware version of `update()`. Components that have been
/// migrated to the timing model should override this method to use `virtual_time`
/// for timing decisions instead of `Instant::now()`.
///
/// The default implementation simply calls `update()`, providing backward compatibility
/// for components that haven't been migrated yet.
///
/// # Parameters
/// - `virtual_time`: Current simulation time in nanoseconds since simulation start.
/// Use this instead of `Instant::now()` for all timing decisions.
fn update_at_time(&mut self, virtual_time: Duration) {
let _ = virtual_time; // Unused by default — backward compatible
self.update();
}
/// Get the timing constraints for this component.
///
/// Returns a `ComponentTiming` struct describing the real-world timing
/// characteristics of this component (access time, setup time, hold time, etc.).
///
/// The default implementation returns zero-constraint timing, which means
/// the component has no timing requirements. Components that have been
/// migrated to the timing model should override this to return their
/// actual hardware timing profile.
fn timing(&self) -> ComponentTiming {
ComponentTiming::default()
}
/// Inject a `VirtualClock` for virtual-time-based operation.
///
/// Components that support the virtual clock timing model should override this
/// method to store the clock. The default implementation is a no-op, so
/// components that don't support virtual clock silently ignore it and fall
/// back to legacy `thread::sleep()` timing in their `run()` method.
///
/// # Parameters
/// - `clock`: The shared `VirtualClock` to use for timing synchronization.
/// Wrapped in `Option` to allow clearing (pass `None` to disconnect).
///
/// # Usage
/// Called by `ConfigurableSystem::inject_virtual_clock()` during system startup.
/// Not intended to be called directly from external code.
fn set_virtual_clock_optional(&mut self, _clock: Option<Arc<VirtualClock>>) {
// Default: no-op — component doesn't support virtual clock
}
/// Check if this component has a VirtualClock injected.
///
/// Returns `true` if `set_virtual_clock_optional()` was called with `Some(clock)`.
/// Used by `ConfigurableSystem::start()` to avoid re-injecting the clock on restart.
///
/// The default implementation returns `false`. Components that support virtual clock
/// should override this to return `true` when their internal `virtual_clock` field is `Some`.
fn has_virtual_clock(&self) -> bool {
false
}
}
/// Extended trait for components that can be run in their own threads
/// Provides automatic thread spawning functionality for components
@ -238,18 +164,9 @@ impl Component for BaseComponent {
self.running.load(Ordering::SeqCst)
}
fn set_running(&mut self, running: bool) {
self.running.store(running, Ordering::SeqCst);
}
fn as_any(&self) -> &dyn Any {
self
}
fn as_any_mut(&mut self) -> &mut dyn Any {
self
}
}
impl RunnableComponent for BaseComponent {}

470
src/component_timing.rs
View file

@ -1,470 +0,0 @@
//! Per-component timing constraints for hardware-accurate simulation.
//!
//! Each `ComponentTiming` instance describes the real timing characteristics of a
//! hardware component. These values are used during simulation to enforce that
//! components behave realistically — for example, ROM won't drive data onto the bus
//! until its access time has elapsed in virtual time.
//!
//! # Hardware Accuracy
//!
//! If the clock is overclocked beyond a component's maximum frequency, or if timing
//! constraints are violated (setup time, hold time, access time), the component will
//! **not** produce correct results — just like real hardware. This is a feature, not
//! a bug: it allows users to observe what happens when they push hardware beyond its
//! limits.
//!
//! # Timing Violations
//!
//! When a timing violation is detected, it is recorded but does not crash the simulation.
//! The component simply produces incorrect or undefined results, as real hardware would.
use std::fmt;
use std::time::Duration;
/// Timing constraints for a hardware component.
///
/// These values are based on datasheet specifications and define the real-world
/// timing behavior that the simulation enforces.
#[derive(Debug, Clone, Copy, PartialEq)]
pub struct ComponentTiming {
/// Human-readable name for this timing profile (e.g., "Intel 4001 ROM").
pub name: &'static str,
/// Time from valid address on the bus to data being available.
///
/// For ROM/RAM: how long after the address is latched until the data output
/// is guaranteed to be valid.
///
/// Intel 4001 ROM: ~500ns
/// Intel 4002 RAM: ~500ns
/// Intel 4003 SR: ~200ns (faster due to simpler design)
pub access_time: Duration,
/// Time from a clock edge until an output signal changes.
///
/// This models the internal gate delay of the component.
/// After a clock edge is detected, the component's output doesn't change
/// instantly — it takes `propagation_delay` nanoseconds.
///
/// Intel 4001 ROM: ~200ns
/// Intel 4002 RAM: ~200ns
/// Intel 4003 SR: ~100ns
pub propagation_delay: Duration,
/// Minimum time that address/data inputs must be stable before a clock edge.
///
/// If the address changes within `setup_time` before a clock edge,
/// the component may latch an incorrect address — just like real hardware.
///
/// Intel 4001 ROM: ~100ns
/// Intel 4002 RAM: ~100ns
pub setup_time: Duration,
/// Minimum time that address/data inputs must remain stable after a clock edge.
///
/// If the address changes within `hold_time` after a clock edge,
/// the component's latched value may be corrupted.
///
/// Intel 4001 ROM: ~50ns
/// Intel 4002 RAM: ~50ns
pub hold_time: Duration,
/// Maximum clock frequency this component supports (in Hz).
///
/// If the clock exceeds this frequency, the component may not complete
/// its internal operations before the next clock edge arrives.
///
/// Intel 4001 ROM: 750 kHz
/// Intel 4002 RAM: 750 kHz
/// Intel 4003 SR: 1 MHz (can handle faster clocks)
pub max_clock_frequency: f64,
/// How frequently (in virtual time) this component's `update_at_time()`
/// should be called. Smaller values = more frequent updates = more accurate
/// but more CPU-intensive.
///
/// This determines how often the component thread wakes up to check for
/// clock edges and timing events.
///
/// Intel 4001 ROM: 100ns (check every 100ns of virtual time)
/// Intel 4003 SR: 50ns (more frequent due to faster timing)
pub min_update_interval: Duration,
}
impl ComponentTiming {
/// Timing profile for the Intel 4001 ROM chip.
///
/// The 4001 is a 256-byte mask-programmable ROM with 4-bit I/O ports.
/// Access time: 500ns from address valid to data output valid.
pub fn intel_4001() -> Self {
ComponentTiming {
name: "Intel 4001 ROM",
access_time: Duration::from_nanos(500),
propagation_delay: Duration::from_nanos(200),
setup_time: Duration::from_nanos(100),
hold_time: Duration::from_nanos(50),
max_clock_frequency: 750_000.0,
min_update_interval: Duration::from_nanos(100),
}
}
/// Timing profile for the Intel 4002 RAM chip.
///
/// The 4002 is a 320-bit dynamic RAM (80 x 4-bit words) with 4-bit output port.
/// Access time: 500ns from address valid to data output valid.
pub fn intel_4002() -> Self {
ComponentTiming {
name: "Intel 4002 RAM",
access_time: Duration::from_nanos(500),
propagation_delay: Duration::from_nanos(200),
setup_time: Duration::from_nanos(100),
hold_time: Duration::from_nanos(50),
max_clock_frequency: 750_000.0,
min_update_interval: Duration::from_nanos(100),
}
}
/// Timing profile for the Intel 4003 shift register.
///
/// The 4003 is a 10-bit static shift register with serial/parallel I/O.
/// Faster access time (200ns) than ROM/RAM due to simpler design.
pub fn intel_4003() -> Self {
ComponentTiming {
name: "Intel 4003 Shift Register",
access_time: Duration::from_nanos(200),
propagation_delay: Duration::from_nanos(100),
setup_time: Duration::from_nanos(50),
hold_time: Duration::from_nanos(30),
max_clock_frequency: 1_000_000.0, // Can handle 1 MHz
min_update_interval: Duration::from_nanos(50),
}
}
/// Timing profile for the Intel 4004 CPU.
///
/// The 4004 is the central processing unit that generates control signals.
/// Its timing is defined by the clock it receives rather than access times.
pub fn intel_4004() -> Self {
ComponentTiming {
name: "Intel 4004 CPU",
access_time: Duration::ZERO, // CPU doesn't have "access time"
propagation_delay: Duration::from_nanos(150),
setup_time: Duration::from_nanos(100),
hold_time: Duration::from_nanos(50),
max_clock_frequency: 750_000.0, // 740 kHz nominal, 750 kHz max
min_update_interval: Duration::from_nanos(100),
}
}
/// Sentinel value representing "no frequency limit".
///
/// Using a large finite value instead of `f64::INFINITY` avoids NaN
/// propagation in downstream arithmetic (e.g., `1.0 / frequency`).
/// 1 PHz (petahertz) is effectively unlimited for any real-world component.
pub const NO_FREQUENCY_LIMIT: f64 = 1_000_000_000_000_000.0; // 1 PHz
/// Timing profile for a generic clock generator.
///
/// Clocks don't have access times — they just toggle at their configured frequency.
pub fn generic_clock() -> Self {
ComponentTiming {
name: "Generic Clock",
access_time: Duration::ZERO,
propagation_delay: Duration::from_nanos(10),
setup_time: Duration::ZERO,
hold_time: Duration::ZERO,
max_clock_frequency: Self::NO_FREQUENCY_LIMIT,
min_update_interval: Duration::from_nanos(50),
}
}
/// Default timing with zero delays (backward-compatible).
///
/// Components that haven't been migrated to the timing model yet
/// use this profile, which imposes no timing constraints.
pub fn default_no_constraints() -> Self {
ComponentTiming {
name: "Default (no constraints)",
access_time: Duration::ZERO,
propagation_delay: Duration::ZERO,
setup_time: Duration::ZERO,
hold_time: Duration::ZERO,
max_clock_frequency: Self::NO_FREQUENCY_LIMIT,
min_update_interval: Duration::from_nanos(100),
}
}
/// Calculate the minimum clock period this component supports.
///
/// Derived from `max_clock_frequency`: period = 1 / frequency.
/// Returns `Duration::ZERO` for components with no practical frequency limit
/// (i.e., `max_clock_frequency >= NO_FREQUENCY_LIMIT`).
pub fn min_clock_period(&self) -> Duration {
if self.max_clock_frequency <= 0.0 || self.max_clock_frequency >= Self::NO_FREQUENCY_LIMIT {
Duration::ZERO
} else {
Duration::from_secs_f64(1.0 / self.max_clock_frequency)
}
}
/// Check if a given clock frequency exceeds this component's maximum.
///
/// Returns `true` if the frequency is within spec, `false` if overclocked.
/// Non-finite values (infinity, NaN) are always rejected.
pub fn supports_frequency(&self, frequency_hz: f64) -> bool {
frequency_hz.is_finite() && frequency_hz <= self.max_clock_frequency
}
/// Check if enough virtual time has elapsed since an event.
///
/// Returns `Ok(())` if `elapsed >= access_time`, `Err(TimingViolation)` otherwise.
pub fn check_access_time(&self, elapsed: Duration) -> Result<(), TimingViolation> {
if elapsed >= self.access_time {
Ok(())
} else {
Err(TimingViolation::AccessTimeNotElapsed {
component: self.name,
required: self.access_time,
actual: elapsed,
})
}
}
/// Check if a signal was stable for the required setup time before a clock edge.
///
/// Returns `Ok(())` if `stability_duration >= setup_time`, `Err(TimingViolation)` otherwise.
pub fn check_setup_time(&self, stability_duration: Duration) -> Result<(), TimingViolation> {
if stability_duration >= self.setup_time {
Ok(())
} else {
Err(TimingViolation::SetupTimeViolation {
component: self.name,
required: self.setup_time,
actual: stability_duration,
})
}
}
/// Check if a signal remained stable for the required hold time after a clock edge.
///
/// Returns `Ok(())` if `stability_duration >= hold_time`, `Err(TimingViolation)` otherwise.
pub fn check_hold_time(&self, stability_duration: Duration) -> Result<(), TimingViolation> {
if stability_duration >= self.hold_time {
Ok(())
} else {
Err(TimingViolation::HoldTimeViolation {
component: self.name,
required: self.hold_time,
actual: stability_duration,
})
}
}
}
impl Default for ComponentTiming {
fn default() -> Self {
Self::default_no_constraints()
}
}
/// A timing violation detected during simulation.
///
/// Timing violations are expected when overclocking or when signals change
/// too quickly. They don't crash the simulation — instead, the component
/// produces incorrect results, just like real hardware.
#[derive(Debug, Clone)]
pub enum TimingViolation {
/// The component's access time has not yet elapsed since the address was latched.
///
/// The data output is not yet valid. Reading the bus now returns undefined data.
AccessTimeNotElapsed {
component: &'static str,
required: Duration,
actual: Duration,
},
/// An input signal did not remain stable for the required setup time
/// before a clock edge.
///
/// The component may have latched an incorrect value.
SetupTimeViolation {
component: &'static str,
required: Duration,
actual: Duration,
},
/// An input signal did not remain stable for the required hold time
/// after a clock edge.
///
/// The component's latched value may be corrupted.
HoldTimeViolation {
component: &'static str,
required: Duration,
actual: Duration,
},
/// The clock frequency exceeds the component's maximum rated frequency.
///
/// The component may not complete its internal operations before the
/// next clock edge arrives.
Overclocked {
component: &'static str,
max_frequency_hz: f64,
actual_frequency_hz: f64,
},
}
impl std::error::Error for TimingViolation {}
impl fmt::Display for TimingViolation {
fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
match self {
TimingViolation::AccessTimeNotElapsed {
component,
required,
actual,
} => write!(
f,
"{}: Access time not elapsed (need {:?}, got {:?})",
component, required, actual
),
TimingViolation::SetupTimeViolation {
component,
required,
actual,
} => write!(
f,
"{}: Setup time violation (need {:?}, got {:?})",
component, required, actual
),
TimingViolation::HoldTimeViolation {
component,
required,
actual,
} => write!(
f,
"{}: Hold time violation (need {:?}, got {:?})",
component, required, actual
),
TimingViolation::Overclocked {
component,
max_frequency_hz,
actual_frequency_hz,
} => write!(
f,
"{}: Overclocked (max {:.0} Hz, actual {:.0} Hz)",
component, max_frequency_hz, actual_frequency_hz
),
}
}
}
#[cfg(test)]
mod tests {
use super::*;
#[test]
fn test_intel_4001_timing() {
let timing = ComponentTiming::intel_4001();
assert_eq!(timing.access_time, Duration::from_nanos(500));
assert_eq!(timing.propagation_delay, Duration::from_nanos(200));
assert_eq!(timing.setup_time, Duration::from_nanos(100));
assert_eq!(timing.hold_time, Duration::from_nanos(50));
assert_eq!(timing.max_clock_frequency, 750_000.0);
}
#[test]
fn test_intel_4003_timing_faster() {
let rom = ComponentTiming::intel_4001();
let sr = ComponentTiming::intel_4003();
// Shift register should be faster than ROM
assert!(sr.access_time < rom.access_time);
assert!(sr.max_clock_frequency > rom.max_clock_frequency);
}
#[test]
fn test_supports_frequency() {
let timing = ComponentTiming::intel_4001();
assert!(timing.supports_frequency(500_000.0)); // 500 kHz — within spec
assert!(timing.supports_frequency(750_000.0)); // 750 kHz — max rated
assert!(!timing.supports_frequency(1_000_000.0)); // 1 MHz — overclocked!
}
#[test]
fn test_check_access_time() {
let timing = ComponentTiming::intel_4001();
// Not enough time elapsed
let result = timing.check_access_time(Duration::from_nanos(300));
assert!(result.is_err());
// Exactly enough time
let result = timing.check_access_time(Duration::from_nanos(500));
assert!(result.is_ok());
// More than enough time
let result = timing.check_access_time(Duration::from_nanos(800));
assert!(result.is_ok());
}
#[test]
fn test_check_setup_time() {
let timing = ComponentTiming::intel_4001();
assert!(timing.check_setup_time(Duration::from_nanos(50)).is_err());
assert!(timing.check_setup_time(Duration::from_nanos(100)).is_ok());
assert!(timing.check_setup_time(Duration::from_nanos(200)).is_ok());
}
#[test]
fn test_overclocking_scenario() {
let rom = ComponentTiming::intel_4001();
let sr = ComponentTiming::intel_4003();
// At 2 MHz clock (500ns cycle, 250ns per phase):
let clock_freq = 2_000_000.0;
let phase_time = Duration::from_nanos(250);
// ROM can't handle 2 MHz
assert!(!rom.supports_frequency(clock_freq));
// ROM access time is 500ns but only gets 250ns per phase
assert!(rom.check_access_time(phase_time).is_err());
// Shift register's access time (200ns) fits within the 250ns phase at 2 MHz,
// but it can't actually handle 2 MHz clock frequency (max 1 MHz).
// We only verify access time here, not frequency support.
assert!(sr.check_access_time(phase_time).is_ok());
}
#[test]
fn test_min_clock_period() {
let timing = ComponentTiming::intel_4001();
let period = timing.min_clock_period();
assert_eq!(period, Duration::from_secs_f64(1.0 / 750_000.0));
}
#[test]
fn test_default_no_constraints() {
let timing = ComponentTiming::default_no_constraints();
assert_eq!(timing.access_time, Duration::ZERO);
// Supports any reasonable finite frequency
assert!(timing.supports_frequency(1_000_000_000.0)); // 1 GHz — well within limit
assert!(timing.supports_frequency(999_999_999_999_999.0)); // Just under sentinel
assert!(!timing.supports_frequency(f64::INFINITY)); // Non-finite rejected
assert!(!timing.supports_frequency(f64::NAN)); // NaN rejected
}
#[test]
fn test_timing_violation_display() {
let violation = TimingViolation::AccessTimeNotElapsed {
component: "Intel 4001 ROM",
required: Duration::from_nanos(500),
actual: Duration::from_nanos(250),
};
let display = format!("{}", violation);
assert!(display.contains("Access time not elapsed"));
assert!(display.contains("Intel 4001 ROM"));
}
}

249
src/components/clock/generic_clock.rs
View file

@ -1,27 +1,21 @@
use parking_lot::Mutex;
use std::any::Any;
use std::collections::HashMap;
use std::sync::Arc;
use std::sync::{Arc, Mutex};
use std::thread;
use std::time::Duration;
use std::time::{Duration, Instant};
use crate::component::{BaseComponent, Component};
use crate::component_timing::ComponentTiming;
use crate::pin::{Pin, PinValue};
use crate::virtual_clock::VirtualClock;
pub struct GenericClock {
base: BaseComponent,
frequency: f64, // Frequency in Hz
duty_cycle: f64, // Duty cycle as percentage (0.0 to 1.0)
current_state: PinValue,
last_transition_vtime: Duration, // Virtual time of last phase transition
last_transition: Instant,
high_time: Duration,
low_time: Duration,
enabled: bool,
paused: bool, // Pause state for system control
pause_start_vtime: Option<Duration>, // Virtual time when pause started
virtual_clock: Option<Arc<VirtualClock>>, // Injected by ConfigurableSystem (Phase 7)
}
impl GenericClock {
@ -34,39 +28,16 @@ impl GenericClock {
frequency,
duty_cycle: 0.5, // 50% duty cycle by default
current_state: PinValue::Low,
last_transition_vtime: Duration::ZERO,
last_transition: Instant::now(),
high_time: Duration::from_secs_f64(0.5 / frequency), // Will be recalculated in set_duty_cycle
low_time: Duration::from_secs_f64(0.5 / frequency), // Will be recalculated in set_duty_cycle
enabled: true,
paused: false,
pause_start_vtime: None,
virtual_clock: None,
};
clock.set_duty_cycle(0.5); // Initialize timing
clock
}
/// Inject a VirtualClock for virtual-time-based operation.
/// If not set, the clock falls back to wall-clock Instant-based timing
/// via `run_legacy()`. This method is called by ConfigurableSystem in Phase 7.
pub fn set_virtual_clock(&mut self, clock: Arc<VirtualClock>) {
self.virtual_clock = Some(clock);
}
/// Set the clock frequency dynamically
pub fn set_frequency(&mut self, frequency: f64) {
if frequency > 0.0 {
self.frequency = frequency;
self.update_timing();
}
}
/// Get the current clock frequency
pub fn get_frequency(&self) -> f64 {
self.frequency
}
pub fn set_duty_cycle(&mut self, duty_cycle: f64) {
self.duty_cycle = duty_cycle.clamp(0.1, 0.9); // Keep within reasonable bounds
self.update_timing();
@ -76,7 +47,7 @@ impl GenericClock {
self.enabled = true;
// Start with known state when enabled
self.current_state = PinValue::Low;
self.last_transition_vtime = self.current_virtual_time();
self.last_transition = Instant::now();
}
pub fn disable(&mut self) {
@ -85,27 +56,6 @@ impl GenericClock {
self.set_clock_output(PinValue::Low);
}
/// Pause the clock - freeze output state
pub fn pause(&mut self) {
self.paused = true;
self.pause_start_vtime = Some(self.current_virtual_time());
}
/// Resume the clock from paused state
pub fn resume(&mut self) {
// No duration adjustment needed — when the system is paused, VirtualClock.pause()
// freezes virtual time, so current_virtual_time() returns the same value it had
// when pause() was called. This means pause_duration would always be zero.
// last_transition_vtime is still correct because virtual time didn't advance.
self.paused = false;
self.pause_start_vtime = None;
}
/// Check if the clock is paused
pub fn is_paused(&self) -> bool {
self.paused
}
fn frequency_to_duration(frequency: f64) -> Duration {
if frequency <= 0.0 {
Duration::from_secs(0)
@ -122,35 +72,23 @@ impl GenericClock {
fn set_clock_output(&self, value: PinValue) {
if let Ok(clock_pin) = self.base.get_pin("CLK") {
let mut pin_guard = clock_pin.lock();
pin_guard.set_driver(Some(self.base.get_name().to_string()), value);
if let Ok(mut pin_guard) = clock_pin.lock() {
pin_guard.set_driver(Some(self.base.get_name().to_string()), value);
}
}
}
fn read_enable_pin(&self) -> bool {
if let Ok(enable_pin) = self.base.get_pin("ENABLE") {
let pin_guard = enable_pin.lock();
return pin_guard.read() == PinValue::High;
if let Ok(pin_guard) = enable_pin.lock() {
return pin_guard.read() == PinValue::High;
}
}
true // Enabled by default if pin doesn't exist or can't be read
}
/// Get current virtual time, or Duration::ZERO if no VirtualClock is injected.
///
/// # Zero-Time Invariant
///
/// Returns `Duration::ZERO` when no VirtualClock is present. In legacy mode,
/// `enable()` sets `last_transition_vtime = ZERO`, and `should_transition()`
/// computes `elapsed = ZERO - ZERO = ZERO`, which is always less than
/// `high_time`/`low_time`, so no spurious transition occurs. This is correct
/// because legacy mode uses `update()` → `update_at_time(ZERO)`.
fn current_virtual_time(&self) -> Duration {
self.virtual_clock.as_ref().map_or(Duration::ZERO, |vc| vc.now())
}
/// Check if enough virtual time has elapsed for a phase transition.
fn should_transition(&self, virtual_time: Duration) -> bool {
let elapsed = virtual_time.saturating_sub(self.last_transition_vtime);
fn should_transition(&self) -> bool {
let elapsed = self.last_transition.elapsed();
match self.current_state {
PinValue::High => elapsed >= self.high_time,
@ -159,8 +97,7 @@ impl GenericClock {
}
}
/// Perform a phase transition at the given virtual time.
fn perform_transition(&mut self, virtual_time: Duration) {
fn perform_transition(&mut self) {
let new_state = match self.current_state {
PinValue::High => PinValue::Low,
PinValue::Low => PinValue::High,
@ -169,22 +106,46 @@ impl GenericClock {
self.current_state = new_state;
self.set_clock_output(new_state);
self.last_transition_vtime = virtual_time;
self.last_transition = Instant::now();
}
}
impl Component for GenericClock {
fn name(&self) -> String {
self.base.name()
}
/// Calculate the virtual time of the next phase transition.
fn next_transition_time(&self) -> Duration {
let phase_duration = match self.current_state {
PinValue::High => self.high_time,
PinValue::Low => self.low_time,
PinValue::HighZ => Duration::from_nanos(1),
};
self.last_transition_vtime.saturating_add(phase_duration)
fn pins(&self) -> HashMap<String, Arc<Mutex<Pin>>> {
self.base.pins()
}
/// Legacy run loop using wall-clock time (backward compatibility).
/// Used when no VirtualClock has been injected.
fn run_legacy(&mut self) {
fn get_pin(&self, name: &str) -> Result<Arc<Mutex<Pin>>, String> {
self.base.get_pin(name)
}
fn update(&mut self) {
// Read external enable control
let external_enable = self.read_enable_pin();
let should_be_enabled = self.enabled && external_enable;
if !should_be_enabled {
if self.current_state != PinValue::Low {
self.set_clock_output(PinValue::Low);
self.current_state = PinValue::Low;
}
return;
}
// Check if it's time to transition
if self.should_transition() {
self.perform_transition();
}
}
fn run(&mut self) {
self.base.set_running(true);
self.enable(); // Ensure clock is enabled when running
while self.is_running() {
self.update();
@ -202,88 +163,6 @@ impl GenericClock {
// Clean up when stopping
self.disable();
}
}
impl Component for GenericClock {
fn name(&self) -> String {
self.base.name()
}
fn pins(&self) -> HashMap<String, Arc<Mutex<Pin>>> {
self.base.pins()
}
fn get_pin(&self, name: &str) -> Result<Arc<Mutex<Pin>>, String> {
self.base.get_pin(name)
}
fn update_at_time(&mut self, virtual_time: Duration) {
// Check pause state first - don't update if paused
if self.paused {
return;
}
// Read external enable control
let external_enable = self.read_enable_pin();
let should_be_enabled = self.enabled && external_enable;
if !should_be_enabled {
if self.current_state != PinValue::Low {
self.set_clock_output(PinValue::Low);
self.current_state = PinValue::Low;
}
return;
}
// Check if it's time to transition (using virtual time)
if self.should_transition(virtual_time) {
self.perform_transition(virtual_time);
}
}
/// Legacy update entry point — delegates to `update_at_time()` with current virtual time.
///
/// **Note:** In legacy mode (no `VirtualClock` injected), `current_virtual_time()` returns
/// `Duration::ZERO`. Since `last_transition_vtime` also starts at `ZERO`, the computed
/// elapsed time is always zero, so `should_transition()` never returns true. This means
/// calling `update()` alone will NOT cause clock transitions in legacy mode — use `run()`
/// (which calls `run_legacy()`) for standalone clock operation.
fn update(&mut self) {
let vtime = self.current_virtual_time();
self.update_at_time(vtime);
}
fn run(&mut self) {
self.base.set_running(true);
self.enable(); // Ensure clock is enabled when running
// If no VirtualClock is injected, fall back to wall-clock run loop
let vclock = match self.virtual_clock.as_ref() {
Some(vc) => Arc::clone(vc),
None => {
return self.run_legacy();
}
};
while self.is_running() {
// Calculate next transition time
let next_transition = self.next_transition_time();
// Block until virtual time reaches next transition
match vclock.wait_until(next_transition) {
Some(current_vtime) => {
if !self.is_running() {
break;
}
self.update_at_time(current_vtime);
}
None => break, // Simulation stopped
}
}
// Clean up when stopping
self.disable();
}
fn stop(&mut self) {
self.base.set_running(false);
@ -294,37 +173,9 @@ impl Component for GenericClock {
self.base.is_running()
}
fn set_running(&mut self, running: bool) {
self.base.set_running(running);
}
fn timing(&self) -> ComponentTiming {
ComponentTiming {
name: "Generic Clock",
access_time: Duration::ZERO,
propagation_delay: Duration::ZERO,
setup_time: Duration::ZERO,
hold_time: Duration::ZERO,
max_clock_frequency: ComponentTiming::NO_FREQUENCY_LIMIT,
min_update_interval: self.high_time.min(self.low_time),
}
}
fn as_any(&self) -> &dyn Any {
self
}
fn as_any_mut(&mut self) -> &mut dyn Any {
self
}
fn set_virtual_clock_optional(&mut self, clock: Option<Arc<VirtualClock>>) {
self.virtual_clock = clock;
}
fn has_virtual_clock(&self) -> bool {
self.virtual_clock.is_some()
}
}
// Advanced clock features

218
src/components/clock/two_phase_clock.rs
View file

@ -1,26 +1,19 @@
use parking_lot::Mutex;
use std::any::Any;
use std::collections::HashMap;
use std::sync::Arc;
use std::sync::{Arc, Mutex};
use std::thread;
use std::time::Duration;
use std::time::{Duration, Instant};
use crate::component::{BaseComponent, Component};
use crate::component_timing::ComponentTiming;
use crate::pin::{Pin, PinValue};
use crate::virtual_clock::VirtualClock;
pub struct TwoPhaseClock {
base: BaseComponent,
phi1_state: PinValue,
phi2_state: PinValue,
last_transition_vtime: Duration, // Virtual time of last phase swap
last_transition: Instant,
phase_time: Duration,
enabled: bool,
paused: bool, // Pause state for system control
pause_start_vtime: Option<Duration>, // Virtual time when pause started
frequency: f64, // Store frequency for dynamic adjustment
virtual_clock: Option<Arc<VirtualClock>>, // Injected by ConfigurableSystem (Phase 7)
}
impl TwoPhaseClock {
@ -38,41 +31,17 @@ impl TwoPhaseClock {
base: BaseComponent::new(name, pins),
phi1_state: PinValue::High, // Start with PHI1 high
phi2_state: PinValue::Low,
last_transition_vtime: Duration::ZERO,
last_transition: Instant::now(),
phase_time,
enabled: true,
paused: false,
pause_start_vtime: None,
frequency,
virtual_clock: None,
}
}
/// Inject a VirtualClock for virtual-time-based operation.
/// If not set, the clock falls back to wall-clock timing via `run_legacy()`.
/// This method is called by ConfigurableSystem in Phase 7.
pub fn set_virtual_clock(&mut self, clock: Arc<VirtualClock>) {
self.virtual_clock = Some(clock);
}
/// Set the clock frequency dynamically
pub fn set_frequency(&mut self, frequency: f64) {
if frequency > 0.0 {
self.frequency = frequency;
self.phase_time = Duration::from_secs_f64(1.0 / frequency / 2.0);
}
}
/// Get the current clock frequency
pub fn get_frequency(&self) -> f64 {
self.frequency
}
pub fn enable(&mut self) {
self.enabled = true;
self.phi1_state = PinValue::High;
self.phi2_state = PinValue::Low;
self.last_transition_vtime = self.current_virtual_time();
self.last_transition = Instant::now();
self.update_outputs();
// Force an immediate update to ensure outputs are driven
@ -86,81 +55,47 @@ impl TwoPhaseClock {
self.update_outputs();
}
/// Pause the clock - freeze output state
pub fn pause(&mut self) {
self.paused = true;
self.pause_start_vtime = Some(self.current_virtual_time());
}
/// Resume the clock from paused state
pub fn resume(&mut self) {
// No duration adjustment needed — when the system is paused, VirtualClock.pause()
// freezes virtual time, so current_virtual_time() returns the same value it had
// when pause() was called. This means pause_duration would always be zero.
// last_transition_vtime is still correct because virtual time didn't advance.
self.paused = false;
self.pause_start_vtime = None;
}
/// Check if the clock is paused
pub fn is_paused(&self) -> bool {
self.paused
}
/// Get current virtual time, or Duration::ZERO if no VirtualClock is injected.
///
/// # Zero-Time Invariant
///
/// Returns `Duration::ZERO` when no VirtualClock is present. In legacy mode,
/// `enable()` sets `last_transition_vtime = ZERO`, and `should_transition()`
/// computes `elapsed = ZERO - ZERO = ZERO`, which is always less than
/// `phase_time`, so no spurious transition occurs.
fn current_virtual_time(&self) -> Duration {
self.virtual_clock.as_ref().map_or(Duration::ZERO, |vc| vc.now())
}
fn update_outputs(&self) {
// Set CLK output (for compatibility)
if let Ok(clk_pin) = self.base.get_pin("CLK") {
let mut pin_guard = clk_pin.lock();
// CLK follows PHI1 for compatibility
pin_guard.set_driver(Some(self.base.get_name().to_string()), self.phi1_state);
if let Ok(mut pin_guard) = clk_pin.lock() {
// CLK follows PHI1 for compatibility
pin_guard.set_driver(Some(self.base.get_name().to_string()), self.phi1_state);
}
}
// Set PHI1 output
if let Ok(phi1_pin) = self.base.get_pin("PHI1") {
let mut pin_guard = phi1_pin.lock();
pin_guard.set_driver(Some(self.base.get_name().to_string()), self.phi1_state);
if let Ok(mut pin_guard) = phi1_pin.lock() {
pin_guard.set_driver(Some(self.base.get_name().to_string()), self.phi1_state);
// Check if pin has connections and trigger propagation
let connection_count = pin_guard.get_connected_pins().len();
if connection_count > 0 {
pin_guard.propagate();
pin_guard.propagate();
// Check if pin has connections and trigger propagation
let connection_count = pin_guard.get_connected_pins().len();
if connection_count > 0 {
pin_guard.propagate();
}
}
}
// Set PHI2 output
if let Ok(phi2_pin) = self.base.get_pin("PHI2") {
let mut pin_guard = phi2_pin.lock();
pin_guard.set_driver(Some(self.base.get_name().to_string()), self.phi2_state);
if let Ok(mut pin_guard) = phi2_pin.lock() {
pin_guard.set_driver(Some(self.base.get_name().to_string()), self.phi2_state);
// Check if pin has connections and trigger propagation
let connection_count = pin_guard.get_connected_pins().len();
if connection_count > 0 {
pin_guard.propagate();
// Check if pin has connections and trigger propagation
let connection_count = pin_guard.get_connected_pins().len();
if connection_count > 0 {
pin_guard.propagate();
}
}
}
}
/// Check if enough virtual time has elapsed for a phase transition.
fn should_transition(&self, virtual_time: Duration) -> bool {
let elapsed = virtual_time.saturating_sub(self.last_transition_vtime);
elapsed >= self.phase_time
fn should_transition(&self) -> bool {
self.last_transition.elapsed() >= self.phase_time
}
/// Perform a phase swap at the given virtual time.
fn perform_transition(&mut self, virtual_time: Duration) {
fn perform_transition(&mut self) {
match (self.phi1_state, self.phi2_state) {
(PinValue::High, PinValue::Low) => {
// PHI1 -> Low, PHI2 -> High
@ -180,25 +115,7 @@ impl TwoPhaseClock {
}
self.update_outputs();
self.last_transition_vtime = virtual_time;
}
/// Legacy run loop using wall-clock time (backward compatibility).
/// Used when no VirtualClock has been injected.
fn run_legacy(&mut self) {
while self.is_running() {
self.update();
// Sleep for a very short time to allow frequent updates
thread::sleep(Duration::from_micros(100)); // 100µs = 10kHz update rate
// Check if should stop
if !self.is_running() {
break;
}
}
self.disable();
self.last_transition = Instant::now();
}
}
@ -215,12 +132,7 @@ impl Component for TwoPhaseClock {
self.base.get_pin(name)
}
fn update_at_time(&mut self, virtual_time: Duration) {
// Check pause state first - don't update if paused
if self.paused {
return;
}
fn update(&mut self) {
if !self.enabled {
return;
}
@ -228,41 +140,35 @@ impl Component for TwoPhaseClock {
// Always update outputs to ensure they're driven
self.update_outputs();
if self.should_transition(virtual_time) {
self.perform_transition(virtual_time);
if self.should_transition() {
// Reduced debug output - only show occasional transitions
// Use atomic counter instead of static mutable for thread safety
use std::sync::atomic::{AtomicU32, Ordering};
static TRANSITION_COUNT: AtomicU32 = AtomicU32::new(0);
let count = TRANSITION_COUNT.fetch_add(1, Ordering::Relaxed);
if count % 1000 == 0 {
println!(
"DEBUG: [CLOCK] Transitioning - PHI1: {:?} -> PHI2: {:?} (cycle {})",
self.phi1_state, self.phi2_state, count
);
}
self.perform_transition();
}
}
fn update(&mut self) {
let vtime = self.current_virtual_time();
self.update_at_time(vtime);
}
fn run(&mut self) {
self.base.set_running(true);
self.enable();
// If no VirtualClock is injected, fall back to wall-clock run loop
let vclock = match self.virtual_clock.as_ref() {
Some(vc) => Arc::clone(vc),
None => {
return self.run_legacy();
}
};
while self.is_running() {
// Calculate next transition time
let next_transition = self.last_transition_vtime + self.phase_time;
self.update();
// Block until virtual time reaches next transition
match vclock.wait_until(next_transition) {
Some(current_vtime) => {
if !self.is_running() {
break;
}
self.update_at_time(current_vtime);
}
None => break, // Simulation stopped
// Sleep for a very short time to allow frequent updates
thread::sleep(Duration::from_micros(100)); // 100µs = 10kHz update rate
// Check if should stop
if !self.is_running() {
break;
}
}
@ -278,35 +184,7 @@ impl Component for TwoPhaseClock {
self.base.is_running()
}
fn set_running(&mut self, running: bool) {
self.base.set_running(running);
}
fn timing(&self) -> ComponentTiming {
ComponentTiming {
name: "Two-Phase Clock",
access_time: Duration::ZERO,
propagation_delay: Duration::ZERO,
setup_time: Duration::ZERO,
hold_time: Duration::ZERO,
max_clock_frequency: ComponentTiming::NO_FREQUENCY_LIMIT,
min_update_interval: self.phase_time,
}
}
fn as_any(&self) -> &dyn Any {
self
}
fn as_any_mut(&mut self) -> &mut dyn Any {
self
}
fn set_virtual_clock_optional(&mut self, clock: Option<Arc<VirtualClock>>) {
self.virtual_clock = clock;
}
fn has_virtual_clock(&self) -> bool {
self.virtual_clock.is_some()
}
}

7
src/components/common/README.md
View file

@ -74,9 +74,8 @@ pub enum Intel400xUnifiedState {
OutputPort, // Intel 4002 (RAM) specific
ShiftData, // Intel 4003 (Shift Register) specific
LoadData, // Intel 4003 (Shift Register) specific
FetchByte1, // Intel 4004 (CPU) specific — fetching first byte
FetchByte2, // Intel 4004 (CPU) specific — fetching second byte of 2-byte instruction
Execute, // Intel 4004 (CPU) specific — executing decoded instruction
FetchInstruction, // Intel 4004 (CPU) specific
ExecuteInstruction, // Intel 4004 (CPU) specific
}
```
@ -293,7 +292,7 @@ The unified state machine operates by:
- **Intel 4001 (ROM)**: Transitions to DriveData to provide read-only data
- **Intel 4002 (RAM)**: Transitions to ReadData, WriteData, or OutputPort based on operation
- **Intel 4003 (Shift Register)**: Ignores address transmission, goes directly to ShiftData
- **Intel 4004 (CPU)**: Uses FetchByte1, FetchByte2, and Execute states for instruction processing
- **Intel 4004 (CPU)**: Uses FetchInstruction and ExecuteInstruction states
## Timing Constants

339
src/components/common/intel_400x.rs
View file

@ -1,6 +1,5 @@
use parking_lot::Mutex;
use std::sync::Arc;
use std::time::Duration;
use std::sync::{Arc, Mutex};
use std::time::{Duration, Instant};
use crate::component::{BaseComponent, Component};
use crate::pin::{Pin, PinValue};
@ -82,8 +81,11 @@ pub trait Intel400xClockHandling {
/// Get a clock pin value safely
fn get_clock_pin(&self, name: &str) -> PinValue {
if let Ok(pin) = self.get_base().get_pin(name) {
let pin_guard = pin.lock();
pin_guard.read_immediate()
if let Ok(pin_guard) = pin.lock() {
pin_guard.read_immediate()
} else {
PinValue::Low
}
} else {
PinValue::Low
}
@ -132,9 +134,10 @@ pub trait Intel400xDataBus {
for i in 0..4 {
if let Ok(pin) = self.get_base().get_pin(&format!("D{}", i)) {
let pin_guard = pin.lock();
if pin_guard.read_immediate() == PinValue::High {
data |= 1 << i;
if let Ok(pin_guard) = pin.lock() {
if pin_guard.read_immediate() == PinValue::High {
data |= 1 << i;
}
}
}
}
@ -149,17 +152,18 @@ pub trait Intel400xDataBus {
for i in 0..4 {
if let Ok(pin) = self.get_base().get_pin(&format!("D{}", i)) {
let mut pin_guard = pin.lock();
let bit_value = (nibble >> i) & 1;
let pin_value = if bit_value == 1 {
PinValue::High
} else {
PinValue::Low
};
pin_guard.set_driver(
Some(format!("{}_DATA", self.get_base().get_name())),
pin_value,
);
if let Ok(mut pin_guard) = pin.lock() {
let bit_value = (nibble >> i) & 1;
let pin_value = if bit_value == 1 {
PinValue::High
} else {
PinValue::Low
};
pin_guard.set_driver(
Some(format!("{}_DATA", self.get_base().get_name())),
pin_value,
);
}
}
}
}
@ -168,11 +172,12 @@ pub trait Intel400xDataBus {
fn tri_state_data_bus(&self) {
for i in 0..4 {
if let Ok(pin) = self.get_base().get_pin(&format!("D{}", i)) {
let mut pin_guard = pin.lock();
pin_guard.set_driver(
Some(format!("{}_DATA", self.get_base().get_name())),
PinValue::HighZ,
);
if let Ok(mut pin_guard) = pin.lock() {
pin_guard.set_driver(
Some(format!("{}_DATA", self.get_base().get_name())),
PinValue::HighZ,
);
}
}
}
}
@ -203,22 +208,14 @@ pub trait Intel400xAddressHandling {
/// After the full address is latched (both nibbles received), the nibbles
/// are cleared to prepare for the next address cycle. The full address
/// should be assembled and stored before calling this function returns.
///
/// # Address Latch Time
///
/// When the address becomes complete (both nibbles latched), this method
/// records `virtual_time` into `address_latch_time`. The caller must provide
/// the current virtual time. See `handle_address_nibble_at()` for a
/// virtual-time-aware alternative that combines nibble handling and latching.
fn handle_address_latching(
&self,
nibble: u8,
address_high_nibble: &mut Option<u8>,
address_low_nibble: &mut Option<u8>,
full_address_ready: &mut bool,
address_latch_time: &mut Option<Duration>,
address_latch_time: &mut Option<Instant>,
_access_time: Duration,
virtual_time: Duration,
) {
if address_high_nibble.is_none() {
// First cycle: latch high nibble (bits 7-4)
@ -226,13 +223,12 @@ pub trait Intel400xAddressHandling {
} else if address_low_nibble.is_none() {
// Second cycle: latch low nibble (bits 3-0)
*address_low_nibble = Some(nibble);
// Mark address as ready
// Mark address as ready and record latch time
*full_address_ready = true;
// Record the virtual time when the address was fully latched.
*address_latch_time = Some(virtual_time);
// Clear nibbles after full address is latched to prepare for next cycle.
// The full address should be assembled from the nibbles before they're cleared
// (e.g., by the caller reading the nibble values before they're cleared).
*address_latch_time = Some(Instant::now());
// Clear nibbles after full address is latched to prepare for next cycle
// The full address should be assembled from the nibbles before this returns
// (e.g., by the caller reading the nibble values before they're cleared)
*address_high_nibble = None;
*address_low_nibble = None;
}
@ -242,12 +238,11 @@ pub trait Intel400xAddressHandling {
/// Returns: true if latency has elapsed
fn handle_latency_wait(
&self,
address_latch_time: &Option<Duration>,
address_latch_time: &Option<Instant>,
access_time: Duration,
virtual_time: Duration,
) -> bool {
if let Some(latch_time) = address_latch_time {
virtual_time.saturating_sub(*latch_time) >= access_time
latch_time.elapsed() >= access_time
} else {
false
}
@ -261,8 +256,11 @@ pub trait Intel400xControlPins {
/// Read SYNC pin state
fn read_sync_pin(&self) -> bool {
if let Ok(pin) = self.get_base().get_pin("SYNC") {
let pin_guard = pin.lock();
pin_guard.read_immediate() == PinValue::High
if let Ok(pin_guard) = pin.lock() {
pin_guard.read_immediate() == PinValue::High
} else {
false
}
} else {
false
}
@ -272,8 +270,11 @@ pub trait Intel400xControlPins {
fn read_cm_rom_pin(&self) -> bool {
// Note: CM pin name varies by component
if let Ok(pin) = self.get_base().get_pin("CM") {
let pin_guard = pin.lock();
pin_guard.read() == PinValue::High
if let Ok(pin_guard) = pin.lock() {
pin_guard.read() == PinValue::High
} else {
false
}
} else {
false
}
@ -282,8 +283,11 @@ pub trait Intel400xControlPins {
/// Read the CI (I/O select) pin state
fn read_ci_pin(&self) -> bool {
if let Ok(pin) = self.get_base().get_pin("CI") {
let pin_guard = pin.lock();
pin_guard.read() == PinValue::High
if let Ok(pin_guard) = pin.lock() {
pin_guard.read() == PinValue::High
} else {
false
}
} else {
false
}
@ -293,8 +297,11 @@ pub trait Intel400xControlPins {
/// Hardware: RESET is active LOW (pin LOW = reset active)
fn read_reset_pin(&self) -> bool {
if let Ok(pin) = self.get_base().get_pin("RESET") {
let pin_guard = pin.lock();
pin_guard.read() == PinValue::Low // Active LOW: LOW means reset is active
if let Ok(pin_guard) = pin.lock() {
pin_guard.read() == PinValue::Low // Active LOW: LOW means reset is active
} else {
false
}
} else {
false
}
@ -310,8 +317,11 @@ pub trait Intel400xResetHandling {
/// Note: RESET is active LOW (pin LOW = reset active)
fn handle_reset(&mut self, reset_pin_name: &str) -> bool {
let reset = if let Ok(pin) = self.get_base().get_pin(reset_pin_name) {
let pin_guard = pin.lock();
pin_guard.read() == PinValue::Low // Active LOW: LOW means reset is active
if let Ok(pin_guard) = pin.lock() {
pin_guard.read() == PinValue::Low // Active LOW: LOW means reset is active
} else {
false
}
} else {
false
};
@ -331,8 +341,8 @@ pub trait Intel400xResetHandling {
pub trait Intel400xTimingState {
fn get_timing_state(&self) -> MemoryState;
fn set_timing_state(&mut self, state: MemoryState);
fn get_address_latch_time(&self) -> Option<Duration>;
fn set_address_latch_time(&mut self, time: Option<Duration>);
fn get_address_latch_time(&self) -> Option<Instant>;
fn set_address_latch_time(&mut self, time: Option<Instant>);
fn get_full_address_ready(&self) -> bool;
fn set_full_address_ready(&mut self, ready: bool);
fn get_address_high_nibble(&self) -> Option<u8>;
@ -340,10 +350,6 @@ pub trait Intel400xTimingState {
fn get_address_low_nibble(&self) -> Option<u8>;
fn set_address_low_nibble(&mut self, nibble: Option<u8>);
fn get_access_time(&self) -> Duration;
/// Check if latency has elapsed at a given virtual time.
/// Returns true if `virtual_time - address_latch_time >= access_time`.
fn is_latency_elapsed_at(&self, virtual_time: Duration) -> bool;
}
/// Component type enumeration for Intel 400x series
@ -586,11 +592,10 @@ pub enum Intel400xEvent {
///
/// # Example
///
/// ```rust
/// ```rust,ignore
/// use std::time::Duration;
/// use rusty_emu::components::common::intel_400x::{
/// Intel400xComponentBehavior, Intel400xComponentType, Intel400xUnifiedState,
/// Intel400xEvent
/// Intel400xComponentBehavior, Intel400xComponentType, Intel400xUnifiedState
/// };
///
/// struct MyCustomComponent {
@ -614,23 +619,7 @@ pub enum Intel400xEvent {
/// }
/// }
///
/// fn on_state_exit(&mut self, _state: Intel400xUnifiedState) {
/// // Cleanup when exiting a state
/// }
///
/// fn handle_component_event(&mut self, _event: Intel400xEvent) -> bool {
/// // Return true to handle event, false to let state machine process it
/// false
/// }
///
/// fn execute_state_logic(&mut self, _state: Intel400xUnifiedState) {
/// // Execute state-specific logic
/// }
///
/// fn responds_to_address(&self) -> bool {
/// // Most components respond to address transmission
/// true
/// }
/// // ... implement other methods
/// }
/// ```
pub trait Intel400xComponentBehavior {
@ -657,10 +646,7 @@ pub trait Intel400xComponentBehavior {
///
/// # Example
///
/// ```rust,no_run
/// use rusty_emu::components::common::intel_400x::Intel400xUnifiedState;
/// # struct MyComponent { address_high_nibble: Option<u8>, address_low_nibble: Option<u8> }
/// # impl MyComponent {
/// ```rust,ignore
/// fn on_state_entry(&mut self, state: Intel400xUnifiedState) {
/// match state {
/// Intel400xUnifiedState::AddressPhase => {
@ -670,12 +656,11 @@ pub trait Intel400xComponentBehavior {
/// }
/// Intel400xUnifiedState::DriveData => {
/// // Prepare data for output
/// // self.prepare_output_data();
/// self.prepare_output_data();
/// }
/// _ => {}
/// }
/// }
/// # }
/// ```
fn on_state_entry(&mut self, state: Intel400xUnifiedState);
@ -719,14 +704,7 @@ pub trait Intel400xComponentBehavior {
///
/// # Example
///
/// ```rust,no_run
/// use rusty_emu::components::common::intel_400x::Intel400xUnifiedState;
/// # struct MyComponent { current_address: u16 }
/// # impl MyComponent {
/// # fn read_data_bus(&self) -> u8 { 0 }
/// # fn latch_address_nibble(&mut self, _nibble: u8) {}
/// # fn read_memory(&self, _addr: u16) -> u8 { 0 }
/// # fn write_data_bus(&self, _data: u8) {}
/// ```rust,ignore
/// fn execute_state_logic(&mut self, state: Intel400xUnifiedState) {
/// match state {
/// Intel400xUnifiedState::AddressPhase => {
@ -742,7 +720,6 @@ pub trait Intel400xComponentBehavior {
/// _ => {}
/// }
/// }
/// # }
/// ```
fn execute_state_logic(&mut self, state: Intel400xUnifiedState);
@ -834,8 +811,8 @@ pub struct Intel400xStateMachine {
/// The low nibble (bits 3-0) of the currently latching address
address_low_nibble: Option<u8>,
/// The time when the address was completely latched (virtual time in nanoseconds)
address_latch_time: Option<Duration>,
/// The time when the address was completely latched
address_latch_time: Option<Instant>,
/// The access time to wait after address latching before data access
access_time: Duration,
@ -926,13 +903,13 @@ impl Intel400xStateMachine {
self.address_low_nibble = nibble;
}
/// Get address latch time (virtual time)
pub fn get_address_latch_time(&self) -> Option<Duration> {
/// Get address latch time
pub fn get_address_latch_time(&self) -> Option<Instant> {
self.address_latch_time
}
/// Set address latch time (virtual time)
pub fn set_address_latch_time(&mut self, time: Option<Duration>) {
/// Set address latch time
pub fn set_address_latch_time(&mut self, time: Option<Instant>) {
self.address_latch_time = time;
}
@ -959,31 +936,17 @@ impl Intel400xStateMachine {
self.address_latch_time = None;
}
/// Handle address nibble latching (legacy — uses Duration::ZERO as latch time).
/// Returns true only when BOTH nibbles have been latched (address complete).
///
/// **Deprecated:** Use [`handle_address_nibble_at(virtual_time)`](Self::handle_address_nibble_at)
/// instead, which records the actual virtual time when the address is complete.
/// This method sets `address_latch_time` to `Duration::ZERO` as a fallback, so
/// `is_latency_elapsed_at()` will return `true` once any virtual time >= access_time
/// has passed — which is sufficient for most use cases but less precise than
/// `handle_address_nibble_at()`.
#[deprecated(
since = "0.1.0",
note = "Use handle_address_nibble_at(nibble, virtual_time) instead."
)]
/// Handle address nibble latching
/// Returns true only when BOTH nibbles have been latched (address complete)
pub fn handle_address_nibble(&mut self, nibble: u8) -> bool {
if self.address_high_nibble.is_none() {
// First cycle: latch high nibble (bits 7-4)
self.address_high_nibble = Some(nibble);
false // Address not complete yet - still need low nibble
} else if self.address_low_nibble.is_none() {
// Second cycle: latch low nibble (bits 3-0)
// Second cycle: latch low nibble (bits 3-0) and transition to latency wait
self.address_low_nibble = Some(nibble);
// Set fallback latch time so is_latency_elapsed_at() doesn't hang forever.
// Duration::ZERO means "latency started at the beginning of time", so any
// positive virtual time >= access_time will satisfy the latency check.
self.address_latch_time = Some(Duration::ZERO);
self.address_latch_time = Some(Instant::now());
true // Address complete - both nibbles latched
} else {
// Address already latched, ignore
@ -991,52 +954,10 @@ impl Intel400xStateMachine {
}
}
/// Handle address nibble latching with virtual time.
/// Returns true only when BOTH nibbles have been latched (address complete).
/// Records address_latch_time as virtual_time when complete.
pub fn handle_address_nibble_at(&mut self, nibble: u8, virtual_time: Duration) -> bool {
if self.address_high_nibble.is_none() {
// First cycle: latch high nibble (bits 7-4)
self.address_high_nibble = Some(nibble);
false // Address not complete yet - still need low nibble
} else if self.address_low_nibble.is_none() {
// Second cycle: latch low nibble (bits 3-0) and record virtual time
self.address_low_nibble = Some(nibble);
self.address_latch_time = Some(virtual_time);
true // Address complete - both nibbles latched
} else {
// Address already latched, ignore
false
}
}
/// Check if latency has elapsed (legacy — returns false without virtual time).
///
/// This method existed in the `Instant`-based timing model and cannot be emulated
/// with virtual time because the caller must provide the current virtual time.
///
/// Use [`is_latency_elapsed_at(virtual_time)`](Self::is_latency_elapsed_at) instead.
///
/// # Return Value
/// Always returns `false` since virtual time is not available. This is a safe
/// fallback that prevents incorrect behavior — without virtual time, we cannot
/// confirm latency has elapsed, so we conservatively return false.
#[deprecated(
since = "0.1.0",
note = "Use is_latency_elapsed_at(virtual_time) instead. \
This method always returns false without virtual time."
)]
/// Check if latency has elapsed
pub fn is_latency_elapsed(&self) -> bool {
// Cannot determine latency without virtual time — conservatively return false.
// The #[deprecated] attribute produces compile-time warnings; no runtime spam needed.
false
}
/// Check if latency has elapsed at a given virtual time.
/// Returns true if `virtual_time - address_latch_time >= access_time`.
pub fn is_latency_elapsed_at(&self, virtual_time: Duration) -> bool {
if let Some(latch_time) = self.address_latch_time {
virtual_time.saturating_sub(latch_time) >= self.access_time
latch_time.elapsed() >= self.access_time
} else {
false
}
@ -1380,26 +1301,36 @@ pub mod utils {
/// Check if a pin value represents a logical high
pub fn is_pin_high(pin: &Arc<Mutex<Pin>>) -> bool {
let pin_guard = pin.lock();
pin_guard.read() == PinValue::High
if let Ok(pin_guard) = pin.lock() {
pin_guard.read() == PinValue::High
} else {
false
}
}
/// Check if a pin value represents high impedance
pub fn is_pin_high_z(pin: &Arc<Mutex<Pin>>) -> bool {
let pin_guard = pin.lock();
pin_guard.read() == PinValue::HighZ
if let Ok(pin_guard) = pin.lock() {
pin_guard.read() == PinValue::HighZ
} else {
false
}
}
/// Safely read a pin value with fallback
pub fn read_pin_safe(pin: &Arc<Mutex<Pin>>, _default: PinValue) -> PinValue {
let pin_guard = pin.lock();
pin_guard.read()
pub fn read_pin_safe(pin: &Arc<Mutex<Pin>>, default: PinValue) -> PinValue {
if let Ok(pin_guard) = pin.lock() {
pin_guard.read()
} else {
default
}
}
/// Safely set a pin driver with error handling
pub fn set_pin_driver_safe(pin: &Arc<Mutex<Pin>>, driver_name: String, value: PinValue) {
let mut pin_guard = pin.lock();
pin_guard.set_driver(Some(driver_name), value);
if let Ok(mut pin_guard) = pin.lock() {
pin_guard.set_driver(Some(driver_name), value);
}
}
}
@ -1494,50 +1425,27 @@ mod tests {
// First nibble should latch high nibble but NOT complete the address
// Returns false because we still need the low nibble
assert!(!sm.handle_address_nibble_at(0xA, Duration::from_nanos(100)));
assert!(!sm.handle_address_nibble(0xA));
assert_eq!(sm.get_address_high_nibble(), Some(0xA));
assert_eq!(sm.get_address_low_nibble(), None);
assert!(!sm.is_full_address_ready());
// Second nibble should latch low nibble and complete address
// Returns true because address is now complete
// address_latch_time is recorded at virtual_time=200ns
assert!(sm.handle_address_nibble_at(0x5, Duration::from_nanos(200)));
assert!(sm.handle_address_nibble(0x5));
assert_eq!(sm.get_address_high_nibble(), Some(0xA));
assert_eq!(sm.get_address_low_nibble(), Some(0x5));
assert!(sm.is_full_address_ready());
assert_eq!(sm.get_full_address(), Some(0xA5));
// address_latch_time is now set by handle_address_nibble_at()
assert_eq!(sm.get_address_latch_time(), Some(Duration::from_nanos(200)));
assert!(sm.get_address_latch_time().is_some());
// Address already latched should not change anything
assert!(!sm.handle_address_nibble_at(0x3, Duration::from_nanos(300)));
assert!(!sm.handle_address_nibble(0x3));
assert_eq!(sm.get_address_high_nibble(), Some(0xA));
assert_eq!(sm.get_address_low_nibble(), Some(0x5));
assert!(sm.is_full_address_ready());
assert_eq!(sm.get_full_address(), Some(0xA5));
}
#[test]
fn test_address_latching_with_virtual_time() {
let mut sm = Intel400xStateMachine::new(
Intel400xComponentType::Intel4001,
Duration::from_nanos(500),
);
// First nibble with virtual time
assert!(!sm.handle_address_nibble_at(0xA, Duration::from_nanos(100)));
assert_eq!(sm.get_address_high_nibble(), Some(0xA));
// Second nibble with virtual time — should set address_latch_time
assert!(sm.handle_address_nibble_at(0x5, Duration::from_nanos(200)));
assert_eq!(sm.get_full_address(), Some(0xA5));
assert_eq!(sm.get_address_latch_time(), Some(Duration::from_nanos(200)));
// Latency should NOT be elapsed at 200ns (need 500ns)
assert!(!sm.is_latency_elapsed_at(Duration::from_nanos(400)));
// Latency SHOULD be elapsed at 700ns (700 - 200 = 500ns >= 500ns)
assert!(sm.is_latency_elapsed_at(Duration::from_nanos(700)));
assert!(sm.get_address_latch_time().is_some());
}
#[test]
@ -1630,18 +1538,18 @@ mod tests {
);
let mut behavior = MockComponentBehavior::new(Intel400xComponentType::Intel4001);
// Initially no latency should be elapsed (no address latched)
assert!(!sm.is_latency_elapsed_at(Duration::ZERO));
// Initially no latency should be elapsed
assert!(!sm.is_latency_elapsed());
// Latch an address using virtual time
sm.handle_address_nibble_at(0xA, Duration::from_nanos(100));
sm.handle_address_nibble_at(0x5, Duration::from_nanos(200));
// Latch an address
sm.handle_address_nibble(0xA);
sm.handle_address_nibble(0x5);
// Initially latency should not be elapsed (need to wait for access time)
assert!(!sm.is_latency_elapsed());
// Initially latency should not be elapsed (need to wait for access time = 1ms)
assert!(!sm.is_latency_elapsed_at(Duration::from_micros(500)));
// At 1.2ms virtual time, latency should be elapsed (1200 - 200 = 1000us >= 1ms)
assert!(sm.is_latency_elapsed_at(Duration::from_micros(1200)));
// Wait for latency to elapse
std::thread::sleep(Duration::from_millis(2));
assert!(sm.is_latency_elapsed());
// First need to transition to AddressPhase state
process_event_direct(&mut sm, Intel400xEvent::ChipSelect);
@ -1651,11 +1559,24 @@ mod tests {
process_event_direct(&mut sm, Intel400xEvent::AddressComplete);
assert_eq!(sm.get_state(), Intel400xUnifiedState::WaitLatency);
// Wait for latency to elapse
std::thread::sleep(Duration::from_millis(2));
assert!(sm.is_latency_elapsed());
// Latency elapsed should transition to DriveData
println!(
"DEBUG: Before LatencyElapsed event, state: {:?}",
sm.get_state()
);
// Ensure state machine is in WaitLatency state before processing LatencyElapsed
assert_eq!(sm.get_state(), Intel400xUnifiedState::WaitLatency);
process_event_direct(&mut sm, Intel400xEvent::LatencyElapsed);
println!(
"DEBUG: After LatencyElapsed event, state: {:?}",
sm.get_state()
);
assert_eq!(sm.get_state(), Intel400xUnifiedState::DriveData);
// Note: behavior.state_entry_called is not called with process_event_direct
// assert!(behavior.state_entry_called);

2378
src/components/cpu/intel_4004.rs
View file

File diff suppressed because it is too large Load diff

89
src/components/cpu/mos_6502.rs
View file

@ -1,7 +1,6 @@
use parking_lot::Mutex;
use std::any::Any;
use std::collections::HashMap;
use std::sync::Arc;
use std::sync::{Arc, Mutex};
use std::thread;
use std::time::Duration;
@ -74,14 +73,15 @@ impl MOS6502 {
fn set_address_bus(&self, address: u16) {
for i in 0..16 {
if let Ok(pin) = self.base.get_pin(&format!("A{}", i)) {
let mut pin_guard = pin.lock();
let bit_value = (address >> i) & 1;
let pin_value = if bit_value == 1 {
PinValue::High
} else {
PinValue::Low
};
pin_guard.set_driver(Some(self.base.get_name().parse().unwrap()), pin_value);
if let Ok(mut pin_guard) = pin.lock() {
let bit_value = (address >> i) & 1;
let pin_value = if bit_value == 1 {
PinValue::High
} else {
PinValue::Low
};
pin_guard.set_driver(Some(self.base.get_name().parse().unwrap()), pin_value);
}
}
}
}
@ -89,23 +89,25 @@ impl MOS6502 {
fn set_data_bus(&self, data: u8) {
for i in 0..8 {
if let Ok(pin) = self.base.get_pin(&format!("D{}", i)) {
let mut pin_guard = pin.lock();
let bit_value = (data >> i) & 1;
let pin_value = if bit_value == 1 {
PinValue::High
} else {
PinValue::Low
};
pin_guard.set_driver(Some(self.base.get_name().parse().unwrap()), pin_value);
if let Ok(mut pin_guard) = pin.lock() {
let bit_value = (data >> i) & 1;
let pin_value = if bit_value == 1 {
PinValue::High
} else {
PinValue::Low
};
pin_guard.set_driver(Some(self.base.get_name().parse().unwrap()), pin_value);
}
}
}
}
fn set_rw_pin(&self, read: bool) {
if let Ok(pin) = self.base.get_pin("RW") {
let mut pin_guard = pin.lock();
let pin_value = if read { PinValue::High } else { PinValue::Low };
pin_guard.set_driver(Some(self.base.get_name().parse().unwrap()), pin_value);
if let Ok(mut pin_guard) = pin.lock() {
let pin_value = if read { PinValue::High } else { PinValue::Low };
pin_guard.set_driver(Some(self.base.get_name().parse().unwrap()), pin_value);
}
}
}
@ -114,9 +116,10 @@ impl MOS6502 {
for i in 0..8 {
if let Ok(pin) = self.base.get_pin(&format!("D{}", i)) {
let pin_guard = pin.lock();
if pin_guard.read() == PinValue::High {
data |= 1 << i;
if let Ok(pin_guard) = pin.lock() {
if pin_guard.read() == PinValue::High {
data |= 1 << i;
}
}
}
}
@ -126,31 +129,43 @@ impl MOS6502 {
pub(crate) fn read_control_pins(&self) -> (bool, bool, bool, bool) {
let irq = if let Ok(pin) = self.base.get_pin("IRQ") {
let pin_guard = pin.lock();
pin_guard.read() == PinValue::Low // IRQ is active low
if let Ok(pin_guard) = pin.lock() {
pin_guard.read() == PinValue::Low // IRQ is active low
} else {
false
}
} else {
false
};
let nmi = if let Ok(pin) = self.base.get_pin("NMI") {
let pin_guard = pin.lock();
pin_guard.read() == PinValue::Low // NMI is active low
if let Ok(pin_guard) = pin.lock() {
pin_guard.read() == PinValue::Low // NMI is active low
} else {
false
}
} else {
false
};
let reset = if let Ok(pin) = self.base.get_pin("RES") {
let pin_guard = pin.lock();
pin_guard.read() == PinValue::Low // RESET is active low
if let Ok(pin_guard) = pin.lock() {
pin_guard.read() == PinValue::Low // RESET is active low
} else {
false
}
} else {
false
};
let rdy = if let Ok(pin) = self.base.get_pin("RDY") {
let pin_guard = pin.lock();
pin_guard.read() == PinValue::High // RDY is active high
if let Ok(pin_guard) = pin.lock() {
pin_guard.read() == PinValue::High // RDY is active high
} else {
true // Default to ready if pin doesn't exist
}
} else {
true // Default to ready if pin doesn't exist
true
};
(irq, nmi, reset, rdy)
@ -218,17 +233,9 @@ impl Component for MOS6502 {
self.is_running
}
fn set_running(&mut self, running: bool) {
self.is_running = running;
}
fn as_any(&self) -> &dyn Any {
self
}
fn as_any_mut(&mut self) -> &mut dyn Any {
self
}
}
// 6502-specific methods

11
src/components/cpu/wdc_65c02.rs
View file

@ -1,7 +1,6 @@
use parking_lot::Mutex;
use std::any::Any;
use std::collections::HashMap;
use std::sync::Arc;
use std::sync::{Arc, Mutex};
use crate::component::Component;
use crate::components::cpu::MOS6502;
@ -110,17 +109,9 @@ impl Component for WDC65C02 {
self.base.is_running()
}
fn set_running(&mut self, running: bool) {
self.base.set_running(running);
}
fn as_any(&self) -> &dyn Any {
self
}
fn as_any_mut(&mut self) -> &mut dyn Any {
self
}
}
// 65C02-specific enhancements

463
src/components/memory/intel_4001.rs
View file

@ -1,12 +1,10 @@
use parking_lot::Mutex;
use std::any::Any;
use std::collections::HashMap;
use std::sync::Arc;
use std::sync::{Arc, Mutex};
use std::thread;
use std::time::Duration;
use std::time::{Duration, Instant};
use crate::component::{BaseComponent, Component, RunnableComponent};
use crate::component_timing::ComponentTiming;
use crate::components::common::intel_400x::{
process_event_direct, Intel400xAddressHandling, Intel400xClockHandling,
Intel400xComponentBehavior, Intel400xComponentType, Intel400xControlPins, Intel400xDataBus,
@ -14,7 +12,6 @@ use crate::components::common::intel_400x::{
Intel400xUnifiedState, TimingState,
};
use crate::pin::{Pin, PinValue};
use crate::virtual_clock::VirtualClock;
/// Intel 4001 - 256-byte ROM with integrated I/O
/// Part of the MCS-4 family, designed to work with Intel 4004 CPU
@ -40,23 +37,6 @@ pub struct Intel4001 {
// Clock edge detection
prev_phi1: PinValue, // Previous Φ1 clock state for edge detection
prev_phi2: PinValue, // Previous Φ2 clock state for edge detection
// M1/M2 data phase tracking
// M1: ROM drives instruction high nibble (OPR, bits 7-4)
// M2: ROM drives instruction low nibble (OPA, bits 3-0)
data_nibble_phase: bool, // false = OPR (high nibble), true = OPA (low nibble)
// A3 wait counter: after latching both address nibbles (A1+A2), the ROM
// must wait one more full clock cycle for the CPU's A3 cycle before driving data.
// This counter tracks how many PHI2 rising edges to wait in WaitLatency.
a3_wait_cycles: u8,
// Track whether data was actually driven during this PHI2 high period
data_driven_this_cycle: bool,
// Virtual time support (Phase 6)
virtual_clock: Option<Arc<VirtualClock>>, // Injected by ConfigurableSystem (Phase 7)
/// Virtual time snapshot for the current update cycle.
/// Set at the start of `update_at_time()` so all internal methods use a
/// consistent time value instead of reading `VirtualClock::now()` which
/// may have advanced since the cycle started.
current_update_time: Duration,
}
#[derive(Debug, Clone, Copy, PartialEq)]
@ -121,10 +101,6 @@ impl Intel400xResetHandling for Intel4001 {
// This is critical for tests that reset the chip between operations
self.prev_phi1 = PinValue::Low;
self.prev_phi2 = PinValue::Low;
// Reset A3 wait counter and data nibble phase
self.a3_wait_cycles = 0;
self.data_nibble_phase = false;
}
}
@ -156,11 +132,11 @@ impl Intel400xTimingState for Intel4001 {
self.state_machine.current_state = unified_state;
}
fn get_address_latch_time(&self) -> Option<Duration> {
fn get_address_latch_time(&self) -> Option<Instant> {
self.state_machine.get_address_latch_time()
}
fn set_address_latch_time(&mut self, time: Option<Duration>) {
fn set_address_latch_time(&mut self, time: Option<Instant>) {
self.state_machine.set_address_latch_time(time);
}
@ -191,10 +167,6 @@ impl Intel400xTimingState for Intel4001 {
fn get_access_time(&self) -> Duration {
self.state_machine.get_access_time()
}
fn is_latency_elapsed_at(&self, virtual_time: Duration) -> bool {
self.state_machine.is_latency_elapsed_at(virtual_time)
}
}
impl Intel400xComponentBehavior for Intel4001 {
@ -207,19 +179,10 @@ impl Intel400xComponentBehavior for Intel4001 {
Intel400xUnifiedState::Idle => {
// Entry actions for Idle state
self.tri_state_data_bus();
// Reset address state for next fetch
self.state_machine.set_address_high_nibble(None);
self.state_machine.set_address_low_nibble(None);
// Reset data driving state for next fetch
self.data_driven_this_cycle = false;
self.data_nibble_phase = false; // Reset to OPR phase
}
Intel400xUnifiedState::AddressPhase => {
// Entry actions for AddressPhase state
// Address latching will happen in execute_state_logic
// Reset address state to ensure clean latch
self.state_machine.set_address_high_nibble(None);
self.state_machine.set_address_low_nibble(None);
}
Intel400xUnifiedState::WaitLatency => {
// Entry actions for WaitLatency state
@ -286,24 +249,9 @@ impl Intel400xComponentBehavior for Intel4001 {
self.handle_address_latching();
}
Intel400xUnifiedState::WaitLatency => {
// Check if latency has elapsed using virtual time.
//
// **With VirtualClock (production):** `address_latch_time` was recorded
// by `handle_address_nibble_at()` in virtual time. We check if enough
// virtual time has elapsed since then (≥ 500ns access time).
//
// **Without VirtualClock (standalone tests):** `current_virtual_time()`
// returns `Duration::ZERO`, so `is_latency_elapsed_at()` would always
// return `false` (since virtual time never advances). The `!has_clock`
// guard short-circuits to skip the wait immediately.
//
// NOTE: The old `Instant::now()`-based code would naturally wait ~500ns
// because wall-clock time always advances. This new code skips the wait
// in legacy mode, making standalone tests less hardware-accurate but
// preventing them from hanging forever in WaitLatency.
let has_clock = self.virtual_clock.is_some();
let vtime = self.current_update_time;
if !has_clock || self.state_machine.is_latency_elapsed_at(vtime) {
// Check if latency has elapsed
if self.state_machine.is_latency_elapsed() {
// Transition to DriveData
self.process_latency_elapsed();
}
}
@ -378,35 +326,9 @@ impl Intel4001 {
),
prev_phi1: PinValue::Low,
prev_phi2: PinValue::Low,
data_nibble_phase: false, // Start with OPR (high nibble)
a3_wait_cycles: 0, // No A3 wait initially
data_driven_this_cycle: false, // No data driven yet
virtual_clock: None,
current_update_time: Duration::ZERO,
}
}
/// Inject a VirtualClock for virtual time-based operation.
/// When set, `update()` uses virtual time and `run()` uses `wait_until()`.
/// This method is called by ConfigurableSystem in Phase 7.
pub fn set_virtual_clock(&mut self, clock: Arc<VirtualClock>) {
self.virtual_clock = Some(clock);
}
/// Get current virtual time, or Duration::ZERO if no VirtualClock is injected.
///
/// # Zero-Time Invariant
///
/// When no VirtualClock is injected, this returns `Duration::ZERO`. The `WaitLatency`
/// handler checks `vtime == Duration::ZERO` to skip latency enforcement in legacy mode.
/// This is intentional: legacy tests don't use VirtualClock and expect latency to be
/// skipped for backward compatibility. If this ever returns a non-zero value without
/// a proper VirtualClock, the latency check would use zero as the latch time and
/// produce incorrect results.
fn current_virtual_time(&self) -> Duration {
self.virtual_clock.as_ref().map_or(Duration::ZERO, |vc| vc.now())
}
/// Set memory access time for simulation
/// Parameters: access_time_ns - Access time in nanoseconds
pub fn set_access_time(&mut self, access_time_ns: u64) {
@ -460,9 +382,10 @@ impl Intel4001 {
for i in 0..4 {
if let Ok(pin) = self.base.get_pin(&format!("IO{}", i)) {
let pin_guard = pin.lock();
if pin_guard.read() == PinValue::High {
data |= 1 << i;
if let Ok(pin_guard) = pin.lock() {
if pin_guard.read() == PinValue::High {
data |= 1 << i;
}
}
}
}
@ -478,7 +401,7 @@ impl Intel4001 {
/// Intel 4004 Address Timing (CPU drives address during PHI1):
/// - A1 cycle: CPU drives PC high nibble on PHI1 rising
/// - A2 cycle: CPU drives PC low nibble on PHI1 rising
/// - ROM latches each nibble on PHI1 RISING edge (CPU has just driven the address)
/// - ROM latches each nibble on PHI1 FALLING edge (after data is stable)
fn handle_phi1_rising(&mut self) {
// Handle system reset first (highest priority)
self.handle_reset("RESET");
@ -498,22 +421,8 @@ impl Intel4001 {
if self.state_machine.get_state() == Intel400xUnifiedState::Idle {
self.process_chip_select();
}
}
// Latch address nibble on PHI1 rising edge
// The CPU drives the address on PHI1 rising, and since CPU update runs
// before ROM update, the address is already on the bus at this point.
if self.state_machine.get_state() == Intel400xUnifiedState::AddressPhase {
let nibble = self.read_data_bus() & 0x0F;
if self.state_machine.handle_address_nibble_at(nibble, self.current_update_time) {
// Address is complete — virtual time was recorded atomically by handle_address_nibble_at()
// Transition to latency wait
let _addr = self.state_machine.get_full_address().unwrap_or(0xFFFF);
self.process_address_complete();
// Set A3 wait counter
self.a3_wait_cycles = 1;
}
// NOTE: Address nibble latching moved to PHI1 falling edge
// This gives the data bus time to stabilize after CPU drives it on PHI1 rising
}
// Handle I/O operations (higher priority than memory operations)
@ -524,33 +433,39 @@ impl Intel4001 {
}
}
/// Handle Φ1 falling edge - No specific action needed
/// Address latching is now done on PHI1 rising edge
/// Handle Φ1 falling edge - Latch address nibbles
/// Hardware: Φ1 low = CPU has finished driving address, data is stable
/// ROM latches address nibbles on PHI1 falling edge to ensure data is stable
fn handle_phi1_falling(&mut self) {
// Address latching moved to PHI1 rising edge
// Only latch if we're in AddressPhase
// Note: We do NOT check chip_select here because:
// 1. Chip select was already verified when we entered AddressPhase
// 2. CM pin may be lowered between A1 and A2 cycles (this is valid)
// 3. Once address phase starts, we must complete both nibbles
// 4. The io_select (CI) pin distinguishes I/O vs memory operations
if self.state_machine.get_state() == Intel400xUnifiedState::AddressPhase {
// Latch address nibble on PHI1 falling edge (data is now stable)
let nibble = self.read_data_bus() & 0x0F;
if self.state_machine.handle_address_nibble(nibble) {
// Address is complete (both nibbles latched), transition to latency wait
self.process_address_complete();
}
}
}
/// Handle Φ2 rising edge - Data phase
/// Hardware: Φ2 high = Peripherals drive bus with data
/// Focus: Data driving operations
fn handle_phi2_rising(&mut self) {
// Handle A3 wait cycle: after address complete, wait one full clock cycle
// for the CPU's A3 cycle before transitioning to DriveData.
// Check for latency elapsed and transition to DriveData if needed
if self.state_machine.get_state() == Intel400xUnifiedState::WaitLatency {
if self.a3_wait_cycles > 0 {
// Still waiting for A3 cycle to complete
self.a3_wait_cycles -= 1;
} else {
// A3 wait complete, transition to DriveData.
// IMPORTANT: Do NOT drive data on this same edge.
// The first data drive happens on the NEXT PHI2 rising edge.
// This ensures the ROM's OPR/OPA phases align with the CPU's M1/M2 cycles.
if self.state_machine.is_latency_elapsed() {
self.process_latency_elapsed();
return; // Skip data driving on this edge
}
}
// Drive data if in DriveData state (only on subsequent PHI2 rising edges)
// Drive data if in DriveData state
if self.state_machine.get_state() == Intel400xUnifiedState::DriveData {
self.handle_data_driving();
}
@ -563,25 +478,9 @@ impl Intel4001 {
fn handle_phi2_falling(&mut self) {
match self.state_machine.get_state() {
Intel400xUnifiedState::DriveData => {
if self.data_driven_this_cycle {
// Data was actually driven this cycle - toggle nibble phase
if !self.data_nibble_phase {
// Just finished OPR (M1), switch to OPA (M2)
self.data_nibble_phase = true;
self.tri_state_data_bus();
// Stay in DriveData for M2 cycle
} else {
// Just finished OPA (M2) - full 8-bit instruction sent
// Return to idle so the next fetch can begin
self.data_nibble_phase = false;
self.tri_state_data_bus();
self.process_operation_complete();
}
} else {
// No data driven this cycle (e.g., just entered DriveData)
// Don't toggle - just tri-state
self.tri_state_data_bus();
}
// End of data phase - tri-state bus and return to idle
self.tri_state_data_bus();
self.process_operation_complete();
}
Intel400xUnifiedState::Idle
@ -600,8 +499,9 @@ impl Intel4001 {
fn tri_state_io_pins(&self) {
for i in 0..4 {
if let Ok(pin) = self.base.get_pin(&format!("IO{}", i)) {
let mut pin_guard = pin.lock();
pin_guard.set_driver(Some(self.base.name()), PinValue::HighZ);
if let Ok(mut pin_guard) = pin.lock() {
pin_guard.set_driver(Some(self.base.name()), PinValue::HighZ);
}
}
}
}
@ -675,8 +575,11 @@ impl Intel4001 {
/// Hardware: CI pin distinguishes I/O vs ROM access when chip selected (CM=1)
fn read_ci_pin(&self) -> bool {
if let Ok(pin) = self.base.get_pin("CI") {
let pin_guard = pin.lock();
pin_guard.read() == PinValue::High
if let Ok(pin_guard) = pin.lock() {
pin_guard.read() == PinValue::High
} else {
false
}
} else {
false
}
@ -717,21 +620,22 @@ impl Intel4001 {
fn update_io_pins(&self) {
for i in 0..4 {
if let Ok(pin) = self.base.get_pin(&format!("IO{}", i)) {
let mut pin_guard = pin.lock();
match self.io_direction[i] {
IoDirection::Output => {
// Drive pin with output port value
let bit_value = (self.io_ports[i]) & 1;
let pin_value = if bit_value == 1 {
PinValue::High
} else {
PinValue::Low
};
pin_guard.set_driver(Some(self.base.name()), pin_value);
}
IoDirection::Input => {
// Input mode - tri-state pin
pin_guard.set_driver(Some(self.base.name()), PinValue::HighZ);
if let Ok(mut pin_guard) = pin.lock() {
match self.io_direction[i] {
IoDirection::Output => {
// Drive pin with output port value
let bit_value = (self.io_ports[i]) & 1;
let pin_value = if bit_value == 1 {
PinValue::High
} else {
PinValue::Low
};
pin_guard.set_driver(Some(self.base.name()), pin_value);
}
IoDirection::Input => {
// Input mode - tri-state pin
pin_guard.set_driver(Some(self.base.name()), PinValue::HighZ);
}
}
}
}
@ -820,9 +724,8 @@ impl Intel4001 {
// Use common address latching functionality
let nibble = self.read_data_bus() & 0x0F; // Only 4 bits are valid for address nibbles
if self.state_machine.handle_address_nibble_at(nibble, self.current_update_time) {
// Address is complete — virtual time was recorded atomically by handle_address_nibble_at()
// Transition to latency wait
if self.state_machine.handle_address_nibble(nibble) {
// Address is complete, transition to latency wait
self.process_address_complete();
}
}
@ -831,20 +734,18 @@ impl Intel4001 {
/// Hardware: ROM needs 500ns to access data after address is latched
#[allow(dead_code)] // This method is kept for compatibility with legacy code
fn handle_latency_wait(&mut self) {
// Note: Legacy method — latency check now requires virtual time
// Always transition for backward compatibility
self.process_latency_elapsed();
// This is now handled by state machine
if self.state_machine.is_latency_elapsed() {
// Latency elapsed, transition to data driving
// Data will be driven on next Φ2 rising edge
self.process_latency_elapsed();
}
}
/// Handle data driving during DriveData state
/// Hardware: ROM drives data bus when all conditions are met
/// Data stays on bus during Φ2 high period, tri-stated on Φ2 falling edge
/// IMPORTANT: Do NOT return to idle here after OPA - the data must stay on the bus
/// for the CPU to read. Return to idle happens in handle_phi2_falling().
fn handle_data_driving(&mut self) {
// Reset the data-driven flag before each drive attempt
self.data_driven_this_cycle = false;
// Once we're in DriveData state, we should drive data regardless of current control signals
// The control signals were already checked when we started memory operation
if self.state_machine.is_full_address_ready() {
@ -853,18 +754,8 @@ impl Intel4001 {
let address = self.state_machine.get_full_address().unwrap_or(0) as u16;
if (address as usize) < self.memory.len() {
let data = self.memory[address as usize];
// Intel 4004 data bus is 4 bits wide. Instructions are 8 bits.
// M1 (data_nibble_phase=false): Drive high nibble (OPR, bits 7-4)
// M2 (data_nibble_phase=true): Drive low nibble (OPA, bits 3-0)
let nibble = if self.data_nibble_phase {
data & 0x0F // OPA: low nibble
} else {
(data >> 4) & 0x0F // OPR: high nibble
};
self.write_data_bus(nibble);
self.data_driven_this_cycle = true;
// Do NOT return to idle here! The data must persist on the bus
// for the CPU to read. Return to idle happens in handle_phi2_falling().
self.write_data_bus(data);
// Note: Don't call return_to_idle() here - wait for Φ2 falling edge
} else {
// Invalid address, tri-state
self.tri_state_data_bus();
@ -877,13 +768,13 @@ impl Intel4001 {
/// Helper function to process latency elapsed event
fn process_latency_elapsed(&mut self) {
let old_state = self.state_machine.get_state();
let event = Intel400xEvent::LatencyElapsed;
// Use the process_event_direct function to avoid borrowing conflicts
let new_state = process_event_direct(&mut self.state_machine, event);
// Handle state entry/exit manually
if new_state != old_state {
self.on_state_exit(old_state);
if new_state != self.state_machine.get_state() {
self.on_state_exit(self.state_machine.get_state());
self.state_machine.current_state = new_state;
self.on_state_entry(new_state);
}
@ -891,36 +782,42 @@ impl Intel4001 {
/// Helper function to process chip select event
fn process_chip_select(&mut self) {
let old_state = self.state_machine.get_state();
let event = Intel400xEvent::ChipSelect;
// Use the process_event_direct function to avoid borrowing conflicts
let new_state = process_event_direct(&mut self.state_machine, event);
if new_state != old_state {
self.on_state_exit(old_state);
// Handle state entry/exit manually
if new_state != self.state_machine.get_state() {
self.on_state_exit(self.state_machine.get_state());
self.state_machine.current_state = new_state;
self.on_state_entry(new_state);
}
}
/// Helper function to process operation complete event
fn process_operation_complete(&mut self) {
let old_state = self.state_machine.get_state();
let event = Intel400xEvent::OperationComplete;
// Use the process_event_direct function to avoid borrowing conflicts
let new_state = process_event_direct(&mut self.state_machine, event);
if new_state != old_state {
self.on_state_exit(old_state);
// Handle state entry/exit manually
if new_state != self.state_machine.get_state() {
self.on_state_exit(self.state_machine.get_state());
self.state_machine.current_state = new_state;
self.on_state_entry(new_state);
}
}
/// Helper function to process address complete event
fn process_address_complete(&mut self) {
let old_state = self.state_machine.get_state();
let event = Intel400xEvent::AddressComplete;
// Use the process_event_direct function to avoid borrowing conflicts
let new_state = process_event_direct(&mut self.state_machine, event);
if new_state != old_state {
self.on_state_exit(old_state);
// Handle state entry/exit manually
if new_state != self.state_machine.get_state() {
self.on_state_exit(self.state_machine.get_state());
self.state_machine.current_state = new_state;
self.on_state_entry(new_state);
}
}
@ -949,20 +846,9 @@ impl Component for Intel4001 {
self.base.get_pin(name)
}
/// Main update cycle - delegates to update_at_time with current virtual time
/// Main update cycle - handles clock edge detection and operation dispatch
/// Hardware: Responds to Φ1 and Φ2 clock edges from CPU
fn update(&mut self) {
let vtime = self.current_virtual_time();
self.update_at_time(vtime);
}
/// Virtual-time-aware update cycle - handles clock edge detection and operation dispatch
/// Hardware: Responds to Φ1 and Φ2 clock edges from CPU
fn update_at_time(&mut self, virtual_time: Duration) {
// Snapshot virtual_time for the entire update cycle so internal methods
// (handle_phi1_rising, execute_state_logic, etc.) use a consistent time
// instead of reading VirtualClock::now() which may have advanced.
self.current_update_time = virtual_time;
if !self.is_running() {
return;
}
@ -986,34 +872,30 @@ impl Component for Intel4001 {
}
// Process clock events through component-specific handlers
// IMPORTANT ORDER: Handle falling edges BEFORE rising edges.
// When PHI1 rises and PHI2 falls simultaneously (same half-cycle),
// we must complete the previous operation (PHI2 falling) before
// starting a new one (PHI1 rising). This ensures the ROM returns
// to idle from OPA completion before starting a new address phase.
if phi2_falling {
self.handle_phi2_falling();
// These handlers contain the actual logic for chip select, address latching, etc.
if phi1_rising {
self.handle_phi1_rising();
}
if phi1_falling {
self.handle_phi1_falling();
}
if phi1_rising {
self.handle_phi1_rising();
}
if phi2_rising {
self.handle_phi2_rising();
}
if phi2_falling {
self.handle_phi2_falling();
}
// Note: execute_state_machine() is NOT called here because:
// 1. Address latching is handled directly in handle_phi1_rising()
// 2. Data driving is handled directly in handle_phi2_rising()
// 3. Calling it would cause double-latching of address nibbles
}
/// Run component with VirtualClock support or legacy fallback
/// Run component in time-slice mode (manual control)
/// Hardware: Simulates continuous operation with clock edge detection
fn run(&mut self) {
self.base.set_running(true);
@ -1023,37 +905,13 @@ impl Component for Intel4001 {
self.prev_phi1 = phi1;
self.prev_phi2 = phi2;
// If no VirtualClock is injected, fall back to wall-clock run loop
let vclock = match self.virtual_clock.as_ref() {
Some(vc) => Arc::clone(vc),
None => {
// Legacy mode: use wall-clock timing
while self.is_running() {
self.update();
thread::sleep(Duration::from_micros(1));
}
return;
}
};
// Virtual time mode: wait for next tick to synchronize with clock
while self.is_running() {
let next_tick = vclock.now() + vclock.tick_size();
if let Some(current_vtime) = vclock.wait_until(next_tick) {
self.update_at_time(current_vtime);
} else {
// Clock was interrupted, exit
break;
}
self.update();
// Small delay to prevent busy waiting when no clock is present
thread::sleep(Duration::from_micros(1));
}
}
/// Get timing constraints for Intel 4001 ROM
/// Returns: ComponentTiming with 500ns access time, 200ns propagation delay
fn timing(&self) -> ComponentTiming {
ComponentTiming::intel_4001()
}
/// Stop component and tri-state all outputs
/// Hardware: Component enters low-power state, all pins high-impedance
fn stop(&mut self) {
@ -1068,47 +926,15 @@ impl Component for Intel4001 {
self.base.is_running()
}
fn set_running(&mut self, running: bool) {
self.base.set_running(running);
}
fn as_any(&self) -> &dyn Any {
self
}
fn as_any_mut(&mut self) -> &mut dyn Any {
self
}
fn set_virtual_clock_optional(&mut self, clock: Option<Arc<VirtualClock>>) {
self.virtual_clock = clock;
}
fn has_virtual_clock(&self) -> bool {
self.virtual_clock.is_some()
}
}
impl RunnableComponent for Intel4001 {}
// Intel 4001 specific methods
impl Intel4001 {
/// Debug: get current state machine state name
pub fn debug_state(&self) -> &'static str {
match self.state_machine.get_state() {
Intel400xUnifiedState::Idle => "Idle",
Intel400xUnifiedState::AddressPhase => "AddrPhase",
Intel400xUnifiedState::WaitLatency => "WaitLatency",
Intel400xUnifiedState::DriveData => "DriveData",
_ => "Unknown",
}
}
/// Debug: get current data nibble phase
pub fn debug_nibble_phase(&self) -> bool {
self.data_nibble_phase
}
/// Get ROM size in bytes
/// Returns: Total number of bytes in ROM (256 for 4001)
pub fn get_rom_size(&self) -> usize {
@ -1333,15 +1159,15 @@ mod tests {
// Initialize PHI1 to Low first
{
let mut phi1_guard = phi1_pin.lock();
let mut phi1_guard = phi1_pin.lock().unwrap();
phi1_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
}
// Set up memory read operation: SYNC=1, CM=1, CI=0 (memory access)
{
let mut sync_guard = sync_pin.lock();
let mut cm_guard = cm_pin.lock();
let mut ci_guard = ci_pin.lock();
let mut sync_guard = sync_pin.lock().unwrap();
let mut cm_guard = cm_pin.lock().unwrap();
let mut ci_guard = ci_pin.lock().unwrap();
sync_guard.set_driver(Some("TEST".to_string()), PinValue::High);
cm_guard.set_driver(Some("TEST".to_string()), PinValue::High);
ci_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Memory access
@ -1349,10 +1175,19 @@ mod tests {
// Set Φ1 high (creating rising edge)
{
let mut phi1_guard = phi1_pin.lock();
let mut phi1_guard = phi1_pin.lock().unwrap();
phi1_guard.set_driver(Some("TEST".to_string()), PinValue::High);
}
// Debug: Check pin states before update
println!(
"DEBUG: Before update - SYNC: {:?}, CM: {:?}, CI: {:?}, PHI1: {:?}",
sync_pin.lock().unwrap().read(),
cm_pin.lock().unwrap().read(),
ci_pin.lock().unwrap().read(),
phi1_pin.lock().unwrap().read()
);
// Debug: Check conditions that would trigger memory operation
let sync = rom.read_sync_pin();
let chip_select = rom.read_cm_rom_pin();
@ -1365,6 +1200,20 @@ mod tests {
sync && chip_select && !io_select
);
// Debug: Check edge detection
println!("DEBUG: Before update - prev_phi1: {:?}", rom.prev_phi1);
// Debug: Check what read_clock_pins returns
let (read_phi1, _) = rom.read_clock_pins();
println!("DEBUG: read_clock_pins() returns PHI1: {:?}", read_phi1);
// Debug: Check edge detection logic manually
let phi1_rising = read_phi1 == PinValue::High && rom.prev_phi1 == PinValue::Low;
println!(
"DEBUG: Manual edge detection - PHI1: {:?}, prev_phi1: {:?}, rising: {}",
read_phi1, rom.prev_phi1, phi1_rising
);
// Update to process Φ1 rising edge
rom.update();
@ -1398,9 +1247,9 @@ mod tests {
// Set up memory read operation: SYNC=1, chip_select=1, io_select=0 (memory access)
{
let mut sync_guard = sync_pin.lock();
let mut cm_guard = cm_pin.lock();
let mut ci_guard = ci_pin.lock();
let mut sync_guard = sync_pin.lock().unwrap();
let mut cm_guard = cm_pin.lock().unwrap();
let mut ci_guard = ci_pin.lock().unwrap();
sync_guard.set_driver(Some("TEST".to_string()), PinValue::High);
cm_guard.set_driver(Some("TEST".to_string()), PinValue::High);
ci_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Memory access, not I/O
@ -1433,9 +1282,9 @@ mod tests {
// Set memory operation active
{
let mut sync_guard = sync_pin.lock();
let mut cm_guard = cm_pin.lock();
let mut ci_guard = ci_pin.lock();
let mut sync_guard = sync_pin.lock().unwrap();
let mut cm_guard = cm_pin.lock().unwrap();
let mut ci_guard = ci_pin.lock().unwrap();
sync_guard.set_driver(Some("TEST".to_string()), PinValue::High);
cm_guard.set_driver(Some("TEST".to_string()), PinValue::High);
ci_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Memory access, not I/O
@ -1446,7 +1295,7 @@ mod tests {
// Now assert RESET
{
let mut reset_guard = reset_pin.lock();
let mut reset_guard = reset_pin.lock().unwrap();
reset_guard.set_driver(Some("TEST".to_string()), PinValue::High);
}
@ -1464,10 +1313,10 @@ mod tests {
let d3_pin = rom.get_pin("D3").unwrap();
// After reset, all pins should be HighZ (tri-stated)
assert_eq!(d0_pin.lock().read(), PinValue::HighZ);
assert_eq!(d1_pin.lock().read(), PinValue::HighZ);
assert_eq!(d2_pin.lock().read(), PinValue::HighZ);
assert_eq!(d3_pin.lock().read(), PinValue::HighZ);
assert_eq!(d0_pin.lock().unwrap().read(), PinValue::HighZ);
assert_eq!(d1_pin.lock().unwrap().read(), PinValue::HighZ);
assert_eq!(d2_pin.lock().unwrap().read(), PinValue::HighZ);
assert_eq!(d3_pin.lock().unwrap().read(), PinValue::HighZ);
}
#[test]
@ -1484,19 +1333,19 @@ mod tests {
let d3_pin = rom.get_pin("D3").unwrap();
// Initially, no operation - should be tri-stated
assert_eq!(d0_pin.lock().read(), PinValue::HighZ);
assert_eq!(d1_pin.lock().read(), PinValue::HighZ);
assert_eq!(d2_pin.lock().read(), PinValue::HighZ);
assert_eq!(d3_pin.lock().read(), PinValue::HighZ);
assert_eq!(d0_pin.lock().unwrap().read(), PinValue::HighZ);
assert_eq!(d1_pin.lock().unwrap().read(), PinValue::HighZ);
assert_eq!(d2_pin.lock().unwrap().read(), PinValue::HighZ);
assert_eq!(d3_pin.lock().unwrap().read(), PinValue::HighZ);
// Set up memory operation but don't complete address phase
let sync_pin = rom.get_pin("SYNC").unwrap();
let cm_pin = rom.get_pin("CM").unwrap();
let ci_pin = rom.get_pin("CI").unwrap();
let mut sync_guard = sync_pin.lock();
let mut cm_guard = cm_pin.lock();
let mut ci_guard = ci_pin.lock();
let mut sync_guard = sync_pin.lock().unwrap();
let mut cm_guard = cm_pin.lock().unwrap();
let mut ci_guard = ci_pin.lock().unwrap();
sync_guard.set_driver(Some("TEST".to_string()), PinValue::High);
cm_guard.set_driver(Some("TEST".to_string()), PinValue::High);
ci_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Memory access, not I/O
@ -1505,20 +1354,20 @@ mod tests {
rom.update();
// Should still be tri-stated during address phase
assert_eq!(d0_pin.lock().read(), PinValue::HighZ);
assert_eq!(d1_pin.lock().read(), PinValue::HighZ);
assert_eq!(d2_pin.lock().read(), PinValue::HighZ);
assert_eq!(d3_pin.lock().read(), PinValue::HighZ);
assert_eq!(d0_pin.lock().unwrap().read(), PinValue::HighZ);
assert_eq!(d1_pin.lock().unwrap().read(), PinValue::HighZ);
assert_eq!(d2_pin.lock().unwrap().read(), PinValue::HighZ);
assert_eq!(d3_pin.lock().unwrap().read(), PinValue::HighZ);
// Complete address phase but don't wait for latency
// Should still be tri-stated
rom.update();
// Should still be tri-stated (waiting for latency)
assert_eq!(d0_pin.lock().read(), PinValue::HighZ);
assert_eq!(d1_pin.lock().read(), PinValue::HighZ);
assert_eq!(d2_pin.lock().read(), PinValue::HighZ);
assert_eq!(d3_pin.lock().read(), PinValue::HighZ);
assert_eq!(d0_pin.lock().unwrap().read(), PinValue::HighZ);
assert_eq!(d1_pin.lock().unwrap().read(), PinValue::HighZ);
assert_eq!(d2_pin.lock().unwrap().read(), PinValue::HighZ);
assert_eq!(d3_pin.lock().unwrap().read(), PinValue::HighZ);
}
#[test]

178
src/components/memory/intel_4002.rs
View file

@ -1,12 +1,10 @@
use parking_lot::Mutex;
use std::any::Any;
use std::collections::HashMap;
use std::sync::Arc;
use std::sync::{Arc, Mutex};
use std::thread;
use std::time::Duration;
use std::time::{Duration, Instant};
use crate::component::{BaseComponent, Component, RunnableComponent};
use crate::component_timing::ComponentTiming;
use crate::components::common::intel_400x::{
process_event_direct, Intel400xAddressHandling, Intel400xClockHandling,
Intel400xComponentBehavior, Intel400xComponentType, Intel400xControlPins, Intel400xDataBus,
@ -14,7 +12,6 @@ use crate::components::common::intel_400x::{
Intel400xUnifiedState, TimingState,
};
use crate::pin::{Pin, PinValue};
use crate::virtual_clock::VirtualClock;
/// Intel 4002 - 320-byte RAM with I/O ports
/// Part of the MCS-4 family, designed to work with Intel 4004 CPU
@ -49,13 +46,6 @@ pub struct Intel4002 {
prev_phi2: PinValue, // Previous Φ2 clock state for edge detection
// Operation type for next cycle (determines ReadData vs WriteData vs OutputPort)
pending_operation: PendingOperation,
// Virtual time support (Phase 6)
virtual_clock: Option<Arc<VirtualClock>>, // Injected by ConfigurableSystem (Phase 7)
/// Virtual time snapshot for the current update cycle.
/// Set at the start of `update_at_time()` so all internal methods use a
/// consistent time value instead of reading `VirtualClock::now()` which
/// may have advanced since the cycle started.
current_update_time: Duration,
}
impl Intel400xClockHandling for Intel4002 {
@ -139,11 +129,11 @@ impl Intel400xTimingState for Intel4002 {
self.state_machine.current_state = unified_state;
}
fn get_address_latch_time(&self) -> Option<Duration> {
fn get_address_latch_time(&self) -> Option<Instant> {
self.state_machine.get_address_latch_time()
}
fn set_address_latch_time(&mut self, time: Option<Duration>) {
fn set_address_latch_time(&mut self, time: Option<Instant>) {
self.state_machine.set_address_latch_time(time);
}
@ -174,10 +164,6 @@ impl Intel400xTimingState for Intel4002 {
fn get_access_time(&self) -> Duration {
self.state_machine.get_access_time()
}
fn is_latency_elapsed_at(&self, virtual_time: Duration) -> bool {
self.state_machine.is_latency_elapsed_at(virtual_time)
}
}
impl Intel400xComponentBehavior for Intel4002 {
@ -277,22 +263,9 @@ impl Intel400xComponentBehavior for Intel4002 {
self.handle_address_latching();
}
Intel400xUnifiedState::WaitLatency => {
// Check if latency has elapsed using virtual time.
//
// **With VirtualClock (production):** `address_latch_time` was recorded
// by `handle_address_nibble_at()` in virtual time. We check if enough
// virtual time has elapsed since then (≥ 500ns access time).
//
// **Without VirtualClock (standalone tests):** `current_virtual_time()`
// returns `Duration::ZERO`, so `is_latency_elapsed_at()` would always
// return `false`. The `!has_clock` guard short-circuits to skip the wait.
//
// NOTE: The old `Instant::now()`-based code would naturally wait ~500ns.
// This new code skips the wait in legacy mode, making standalone tests
// less hardware-accurate but preventing them from hanging in WaitLatency.
let has_clock = self.virtual_clock.is_some();
let vtime = self.current_update_time;
if !has_clock || self.state_machine.is_latency_elapsed_at(vtime) {
// Check if latency has elapsed
if self.state_machine.is_latency_elapsed() {
// Transition to ReadData (default for RAM)
self.process_latency_elapsed();
}
}
@ -375,30 +348,9 @@ impl Intel4002 {
prev_phi1: PinValue::Low,
prev_phi2: PinValue::Low,
pending_operation: PendingOperation::Read, // Default to read
virtual_clock: None,
current_update_time: Duration::ZERO,
}
}
/// Inject a VirtualClock for virtual time-based operation.
/// When set, `update()` uses virtual time and `run()` uses `wait_until()`.
/// This method is called by ConfigurableSystem in Phase 7.
pub fn set_virtual_clock(&mut self, clock: Arc<VirtualClock>) {
self.virtual_clock = Some(clock);
}
/// Get current virtual time, or Duration::ZERO if no VirtualClock is injected.
///
/// # Zero-Time Invariant
///
/// When no VirtualClock is injected, this returns `Duration::ZERO`. The `WaitLatency`
/// handler checks `vtime == Duration::ZERO` to skip latency enforcement in legacy mode.
/// This is intentional: legacy tests don't use VirtualClock and expect latency to be
/// skipped for backward compatibility.
fn current_virtual_time(&self) -> Duration {
self.virtual_clock.as_ref().map_or(Duration::ZERO, |vc| vc.now())
}
/// Set memory access time for simulation
/// Parameters: access_time_ns - Access time in nanoseconds
pub fn set_access_time(&mut self, access_time_ns: u64) {
@ -455,9 +407,11 @@ impl Intel4002 {
fn tri_state_data_bus(&self) {
for i in 0..4 {
if let Ok(pin) = self.base.get_pin(&format!("D{}", i)) {
let mut pin_guard = pin.lock();
// Use the same driver name as write_data_bus() to properly tri-state
pin_guard.set_driver(Some(format!("{}_DATA", self.base.name())), PinValue::HighZ);
if let Ok(mut pin_guard) = pin.lock() {
// Use the same driver name as write_data_bus() to properly tri-state
pin_guard
.set_driver(Some(format!("{}_DATA", self.base.name())), PinValue::HighZ);
}
}
}
}
@ -466,8 +420,9 @@ impl Intel4002 {
fn tri_state_status_pins(&self) {
for i in 0..4 {
if let Ok(pin) = self.base.get_pin(&format!("S{}", i)) {
let mut pin_guard = pin.lock();
pin_guard.set_driver(Some(self.base.name()), PinValue::HighZ);
if let Ok(mut pin_guard) = pin.lock() {
pin_guard.set_driver(Some(self.base.name()), PinValue::HighZ);
}
}
}
}
@ -511,9 +466,8 @@ impl Intel4002 {
// Latch address nibble on PHI1 falling edge (data is now stable)
let nibble = self.read_data_bus() & 0x0F;
if self.state_machine.handle_address_nibble_at(nibble, self.current_update_time) {
// Address is complete — virtual time was recorded atomically by handle_address_nibble_at()
// Transition to latency wait
if self.state_machine.handle_address_nibble(nibble) {
// Address is complete (both nibbles latched), transition to latency wait
self.process_address_complete();
}
}
@ -523,13 +477,9 @@ impl Intel4002 {
/// Hardware: Φ2 high = Peripherals drive bus with data
/// Focus: Data driving operations
fn handle_phi2_rising(&mut self) {
// Check for latency elapsed and transition to ReadData/WriteData/OutputPort if needed.
// When no VirtualClock is injected, skip latency wait for backward compatibility
// (see WaitLatency handler for details).
// Check for latency elapsed and transition to ReadData/WriteData/OutputPort if needed
if self.state_machine.get_state() == Intel400xUnifiedState::WaitLatency {
let has_clock = self.virtual_clock.is_some();
let vtime = self.current_update_time;
if !has_clock || self.state_machine.is_latency_elapsed_at(vtime) {
if self.state_machine.is_latency_elapsed() {
self.process_latency_elapsed();
}
}
@ -586,9 +536,8 @@ impl Intel4002 {
// Use common address latching functionality
let nibble = self.read_data_bus() & 0x0F; // Only 4 bits are valid for address nibbles
if self.state_machine.handle_address_nibble_at(nibble, self.current_update_time) {
// Address is complete — virtual time was recorded atomically by handle_address_nibble_at()
// Transition to latency wait
if self.state_machine.handle_address_nibble(nibble) {
// Address is complete, transition to latency wait
self.process_address_complete();
}
}
@ -666,36 +615,42 @@ impl Intel4002 {
/// Helper function to process chip select event
fn process_chip_select(&mut self) {
let old_state = self.state_machine.get_state();
let event = Intel400xEvent::ChipSelect;
// Use the process_event_direct function to avoid borrowing conflicts
let new_state = process_event_direct(&mut self.state_machine, event);
if new_state != old_state {
self.on_state_exit(old_state);
// Handle state entry/exit manually
if new_state != self.state_machine.get_state() {
self.on_state_exit(self.state_machine.get_state());
self.state_machine.current_state = new_state;
self.on_state_entry(new_state);
}
}
/// Helper function to process operation complete event
fn process_operation_complete(&mut self) {
let old_state = self.state_machine.get_state();
let event = Intel400xEvent::OperationComplete;
// Use the process_event_direct function to avoid borrowing conflicts
let new_state = process_event_direct(&mut self.state_machine, event);
if new_state != old_state {
self.on_state_exit(old_state);
// Handle state entry/exit manually
if new_state != self.state_machine.get_state() {
self.on_state_exit(self.state_machine.get_state());
self.state_machine.current_state = new_state;
self.on_state_entry(new_state);
}
}
/// Helper function to process address complete event
fn process_address_complete(&mut self) {
let old_state = self.state_machine.get_state();
let event = Intel400xEvent::AddressComplete;
// Use the process_event_direct function to avoid borrowing conflicts
let new_state = process_event_direct(&mut self.state_machine, event);
if new_state != old_state {
self.on_state_exit(old_state);
// Handle state entry/exit manually
if new_state != self.state_machine.get_state() {
self.on_state_exit(self.state_machine.get_state());
self.state_machine.current_state = new_state;
self.on_state_entry(new_state);
}
}
@ -714,20 +669,9 @@ impl Component for Intel4002 {
self.base.get_pin(name)
}
/// Main update cycle - delegates to update_at_time with current virtual time
/// Main update cycle - handles clock edge detection and operation dispatch
/// Hardware: Responds to Φ1 and Φ2 clock edges from CPU
fn update(&mut self) {
let vtime = self.current_virtual_time();
self.update_at_time(vtime);
}
/// Virtual-time-aware update cycle - handles clock edge detection and operation dispatch
/// Hardware: Responds to Φ1 and Φ2 clock edges from CPU
fn update_at_time(&mut self, virtual_time: Duration) {
// Snapshot virtual_time for the entire update cycle so internal methods
// use a consistent time instead of reading VirtualClock::now() which
// may have advanced.
self.current_update_time = virtual_time;
if !self.is_running() {
return;
}
@ -774,7 +718,7 @@ impl Component for Intel4002 {
// 3. Calling it would cause double-latching of address nibbles
}
/// Run component with VirtualClock support or legacy fallback
/// Run component in time-slice mode (manual control)
/// Hardware: Simulates continuous operation with clock edge detection
fn run(&mut self) {
self.base.set_running(true);
@ -784,37 +728,13 @@ impl Component for Intel4002 {
self.prev_phi1 = phi1;
self.prev_phi2 = phi2;
// If no VirtualClock is injected, fall back to wall-clock run loop
let vclock = match self.virtual_clock.as_ref() {
Some(vc) => Arc::clone(vc),
None => {
// Legacy mode: use wall-clock timing
while self.is_running() {
self.update();
thread::sleep(Duration::from_micros(1));
}
return;
}
};
// Virtual time mode: wait for next tick to synchronize with clock
while self.is_running() {
let next_tick = vclock.now() + vclock.tick_size();
if let Some(current_vtime) = vclock.wait_until(next_tick) {
self.update_at_time(current_vtime);
} else {
// Clock was interrupted, exit
break;
}
self.update();
// Small delay to prevent busy waiting when no clock is present
thread::sleep(Duration::from_micros(1));
}
}
/// Get timing constraints for Intel 4002 RAM
/// Returns: ComponentTiming with 500ns access time, 200ns propagation delay
fn timing(&self) -> ComponentTiming {
ComponentTiming::intel_4002()
}
/// Stop component and tri-state all outputs
/// Hardware: Component enters low-power state, all pins high-impedance
fn stop(&mut self) {
@ -829,25 +749,9 @@ impl Component for Intel4002 {
self.base.is_running()
}
fn set_running(&mut self, running: bool) {
self.base.set_running(running);
}
fn as_any(&self) -> &dyn Any {
self
}
fn as_any_mut(&mut self) -> &mut dyn Any {
self
}
fn set_virtual_clock_optional(&mut self, clock: Option<Arc<VirtualClock>>) {
self.virtual_clock = clock;
}
fn has_virtual_clock(&self) -> bool {
self.virtual_clock.is_some()
}
}
impl RunnableComponent for Intel4002 {}

173
src/components/memory/intel_4003.rs
View file

@ -1,12 +1,10 @@
use parking_lot::Mutex;
use std::any::Any;
use std::collections::HashMap;
use std::sync::Arc;
use std::sync::{Arc, Mutex};
use std::thread;
use std::time::Duration;
use std::time::{Duration, Instant};
use crate::component::{BaseComponent, Component, RunnableComponent};
use crate::component_timing::ComponentTiming;
use crate::components::common::intel_400x::{
process_event_direct, Intel400xAddressHandling, Intel400xClockHandling,
Intel400xComponentBehavior, Intel400xComponentType, Intel400xControlPins, Intel400xDataBus,
@ -14,7 +12,6 @@ use crate::components::common::intel_400x::{
Intel400xUnifiedState, TimingState,
};
use crate::pin::{Pin, PinValue};
use crate::virtual_clock::VirtualClock;
/// Intel 4003 - 10-bit serial-in, serial-out shift register
/// Part of the MCS-4 family, designed to work with Intel 4004 CPU
@ -35,13 +32,6 @@ pub struct Intel4003 {
// Clock edge detection
prev_phi1: PinValue, // Previous Φ1 clock state for edge detection
prev_phi2: PinValue, // Previous Φ2 clock state for edge detection
// Virtual time support (Phase 6)
virtual_clock: Option<Arc<VirtualClock>>, // Injected by ConfigurableSystem (Phase 7)
/// Virtual time snapshot for the current update cycle.
/// Set at the start of `update_at_time()` so all internal methods use a
/// consistent time value instead of reading `VirtualClock::now()` which
/// may have advanced since the cycle started.
current_update_time: Duration,
}
/// Serial operation modes for 4003 shift register
@ -130,11 +120,11 @@ impl Intel400xTimingState for Intel4003 {
self.state_machine.current_state = unified_state;
}
fn get_address_latch_time(&self) -> Option<Duration> {
fn get_address_latch_time(&self) -> Option<Instant> {
self.state_machine.get_address_latch_time()
}
fn set_address_latch_time(&mut self, time: Option<Duration>) {
fn set_address_latch_time(&mut self, time: Option<Instant>) {
self.state_machine.set_address_latch_time(time);
}
@ -165,10 +155,6 @@ impl Intel400xTimingState for Intel4003 {
fn get_access_time(&self) -> Duration {
self.state_machine.get_access_time()
}
fn is_latency_elapsed_at(&self, virtual_time: Duration) -> bool {
self.state_machine.is_latency_elapsed_at(virtual_time)
}
}
impl Intel400xComponentBehavior for Intel4003 {
@ -256,22 +242,9 @@ impl Intel400xComponentBehavior for Intel4003 {
self.handle_address_latching();
}
Intel400xUnifiedState::WaitLatency => {
// Check if latency has elapsed using virtual time.
//
// **With VirtualClock (production):** `address_latch_time` was recorded
// by `handle_address_nibble_at()` in virtual time. We check if enough
// virtual time has elapsed since then (≥ 200ns access time).
//
// **Without VirtualClock (standalone tests):** `current_virtual_time()`
// returns `Duration::ZERO`, so `is_latency_elapsed_at()` would always
// return `false`. The `!has_clock` guard short-circuits to skip the wait.
//
// NOTE: The old `Instant::now()`-based code would naturally wait ~200ns.
// This new code skips the wait in legacy mode, making standalone tests
// less hardware-accurate but preventing them from hanging in WaitLatency.
let has_clock = self.virtual_clock.is_some();
let vtime = self.current_update_time;
if !has_clock || self.state_machine.is_latency_elapsed_at(vtime) {
// Check if latency has elapsed
if self.state_machine.is_latency_elapsed() {
// Transition to ShiftData (default for 4003)
self.process_latency_elapsed();
}
}
@ -343,30 +316,9 @@ impl Intel4003 {
),
prev_phi1: PinValue::Low,
prev_phi2: PinValue::Low,
virtual_clock: None,
current_update_time: Duration::ZERO,
}
}
/// Inject a VirtualClock for virtual time-based operation.
/// When set, `update()` uses virtual time and `run()` uses `wait_until()`.
/// This method is called by ConfigurableSystem in Phase 7.
pub fn set_virtual_clock(&mut self, clock: Arc<VirtualClock>) {
self.virtual_clock = Some(clock);
}
/// Get current virtual time, or Duration::ZERO if no VirtualClock is injected.
///
/// # Zero-Time Invariant
///
/// When no VirtualClock is injected, this returns `Duration::ZERO`. The `WaitLatency`
/// handler checks `vtime == Duration::ZERO` to skip latency enforcement in legacy mode.
/// This is intentional: legacy tests don't use VirtualClock and expect latency to be
/// skipped for backward compatibility.
fn current_virtual_time(&self) -> Duration {
self.virtual_clock.as_ref().map_or(Duration::ZERO, |vc| vc.now())
}
/// Set access time for simulation
/// Parameters: access_time_ns - Access time in nanoseconds
pub fn set_access_time(&mut self, access_time_ns: u64) {
@ -385,8 +337,9 @@ impl Intel4003 {
fn tri_state_data_bus(&self) {
for i in 0..4 {
if let Ok(pin) = self.base.get_pin(&format!("D{}", i)) {
let mut pin_guard = pin.lock();
pin_guard.set_driver(Some(self.base.name()), PinValue::HighZ);
if let Ok(mut pin_guard) = pin.lock() {
pin_guard.set_driver(Some(self.base.name()), PinValue::HighZ);
}
}
}
}
@ -466,9 +419,8 @@ impl Intel4003 {
// But we still need to handle the address nibble for compatibility
let nibble = self.read_data_bus() & 0x0F; // Only 4 bits are valid for address nibbles
if self.state_machine.handle_address_nibble_at(nibble, self.current_update_time) {
// Address is complete — virtual time was recorded atomically by handle_address_nibble_at()
// Transition to latency wait
if self.state_machine.handle_address_nibble(nibble) {
// Address is complete, transition to latency wait
self.process_address_complete();
}
}
@ -501,48 +453,56 @@ impl Intel4003 {
/// Helper function to process latency elapsed event
fn process_latency_elapsed(&mut self) {
let old_state = self.state_machine.get_state();
let event = Intel400xEvent::LatencyElapsed;
// Use process_event_direct method to avoid borrowing conflicts
let new_state = process_event_direct(&mut self.state_machine, event);
if new_state != old_state {
self.on_state_exit(old_state);
// Handle state entry/exit manually
if new_state != self.state_machine.get_state() {
self.on_state_exit(self.state_machine.get_state());
self.state_machine.current_state = new_state;
self.on_state_entry(new_state);
}
}
/// Helper function to process chip select event
fn process_chip_select(&mut self) {
let old_state = self.state_machine.get_state();
let event = Intel400xEvent::ChipSelect;
// Use process_event_direct method to avoid borrowing conflicts
let new_state = process_event_direct(&mut self.state_machine, event);
if new_state != old_state {
self.on_state_exit(old_state);
// Handle state entry/exit manually
if new_state != self.state_machine.get_state() {
self.on_state_exit(self.state_machine.get_state());
self.state_machine.current_state = new_state;
self.on_state_entry(new_state);
}
}
/// Helper function to process operation complete event
fn process_operation_complete(&mut self) {
let old_state = self.state_machine.get_state();
let event = Intel400xEvent::OperationComplete;
// Use process_event_direct method to avoid borrowing conflicts
let new_state = process_event_direct(&mut self.state_machine, event);
if new_state != old_state {
self.on_state_exit(old_state);
// Handle state entry/exit manually
if new_state != self.state_machine.get_state() {
self.on_state_exit(self.state_machine.get_state());
self.state_machine.current_state = new_state;
self.on_state_entry(new_state);
}
}
/// Helper function to process address complete event
fn process_address_complete(&mut self) {
let old_state = self.state_machine.get_state();
let event = Intel400xEvent::AddressComplete;
// Use process_event_direct method to avoid borrowing conflicts
let new_state = process_event_direct(&mut self.state_machine, event);
if new_state != old_state {
self.on_state_exit(old_state);
// Handle state entry/exit manually
if new_state != self.state_machine.get_state() {
self.on_state_exit(self.state_machine.get_state());
self.state_machine.current_state = new_state;
self.on_state_entry(new_state);
}
}
@ -568,20 +528,9 @@ impl Component for Intel4003 {
self.base.get_pin(name)
}
/// Main update cycle - delegates to update_at_time with current virtual time
/// Main update cycle - handles clock edge detection and operation dispatch
/// Hardware: Responds to Φ1 and Φ2 clock edges from CPU
fn update(&mut self) {
let vtime = self.current_virtual_time();
self.update_at_time(vtime);
}
/// Virtual-time-aware update cycle - handles clock edge detection and operation dispatch
/// Hardware: Responds to Φ1 and Φ2 clock edges from CPU
fn update_at_time(&mut self, virtual_time: Duration) {
// Snapshot virtual_time for the entire update cycle so internal methods
// use a consistent time instead of reading VirtualClock::now() which
// may have advanced.
self.current_update_time = virtual_time;
if !self.is_running() {
return;
}
@ -627,11 +576,13 @@ impl Component for Intel4003 {
// Process all events
for event in events {
let old_state = self.state_machine.get_state();
// Use the process_event_direct method to avoid borrowing conflicts
let new_state = process_event_direct(&mut self.state_machine, event);
if new_state != old_state {
self.on_state_exit(old_state);
// Handle state entry/exit manually
if new_state != self.state_machine.get_state() {
self.on_state_exit(self.state_machine.get_state());
self.state_machine.current_state = new_state;
self.on_state_entry(new_state);
}
}
@ -640,7 +591,7 @@ impl Component for Intel4003 {
self.execute_state_machine();
}
/// Run component with VirtualClock support or legacy fallback
/// Run component in time-slice mode (manual control)
/// Hardware: Simulates continuous operation with clock edge detection
fn run(&mut self) {
self.base.set_running(true);
@ -650,37 +601,13 @@ impl Component for Intel4003 {
self.prev_phi1 = phi1;
self.prev_phi2 = phi2;
// If no VirtualClock is injected, fall back to wall-clock run loop
let vclock = match self.virtual_clock.as_ref() {
Some(vc) => Arc::clone(vc),
None => {
// Legacy mode: use wall-clock timing
while self.is_running() {
self.update();
thread::sleep(Duration::from_micros(1));
}
return;
}
};
// Virtual time mode: wait for next tick to synchronize with clock
while self.is_running() {
let next_tick = vclock.now() + vclock.tick_size();
if let Some(current_vtime) = vclock.wait_until(next_tick) {
self.update_at_time(current_vtime);
} else {
// Clock was interrupted, exit
break;
}
self.update();
// Small delay to prevent busy waiting when no clock is present
thread::sleep(Duration::from_micros(1));
}
}
/// Get timing constraints for Intel 4003 shift register
/// Returns: ComponentTiming with 200ns access time, 100ns propagation delay
fn timing(&self) -> ComponentTiming {
ComponentTiming::intel_4003()
}
/// Stop component and tri-state all outputs
/// Hardware: Component enters low-power state, all pins high-impedance
fn stop(&mut self) {
@ -694,25 +621,9 @@ impl Component for Intel4003 {
self.base.is_running()
}
fn set_running(&mut self, running: bool) {
self.base.set_running(running);
}
fn as_any(&self) -> &dyn Any {
self
}
fn as_any_mut(&mut self) -> &mut dyn Any {
self
}
fn set_virtual_clock_optional(&mut self, clock: Option<Arc<VirtualClock>>) {
self.virtual_clock = clock;
}
fn has_virtual_clock(&self) -> bool {
self.virtual_clock.is_some()
}
}
impl RunnableComponent for Intel4003 {}

55
src/connection.rs
View file

@ -1,7 +1,6 @@
use crate::pin::Pin;
use parking_lot::Mutex;
use std::collections::HashMap;
use std::sync::Arc;
use std::sync::{Arc, Mutex};
/// Manages electrical connections between pins
pub struct ConnectionManager {
@ -32,24 +31,32 @@ impl ConnectionManager {
pin2: Arc<Mutex<Pin>>,
) -> Result<(), String> {
let pin1_name = {
let p1 = pin1.lock();
let p1 = pin1
.lock()
.map_err(|e| format!("Failed to lock pin1: {}", e))?;
p1.name().to_string()
};
let pin2_name = {
let p2 = pin2.lock();
let p2 = pin2
.lock()
.map_err(|e| format!("Failed to lock pin2: {}", e))?;
p2.name().to_string()
};
// Connect pin1 to pin2
{
let mut p1 = pin1.lock();
let mut p1 = pin1
.lock()
.map_err(|e| format!("Failed to lock pin1: {}", e))?;
p1.connect_to(pin2.clone());
}
// Connect pin2 to pin1 (bidirectional)
{
let mut p2 = pin2.lock();
let mut p2 = pin2
.lock()
.map_err(|e| format!("Failed to lock pin2: {}", e))?;
p2.connect_to(pin1.clone());
}
@ -89,24 +96,32 @@ impl ConnectionManager {
pin2: &Arc<Mutex<Pin>>,
) -> Result<(), String> {
let pin1_name = {
let p1 = pin1.lock();
let p1 = pin1
.lock()
.map_err(|e| format!("Failed to lock pin1: {}", e))?;
p1.name().to_string()
};
let pin2_name = {
let p2 = pin2.lock();
let p2 = pin2
.lock()
.map_err(|e| format!("Failed to lock pin2: {}", e))?;
p2.name().to_string()
};
// Disconnect pin1 from pin2
{
let mut p1 = pin1.lock();
let mut p1 = pin1
.lock()
.map_err(|e| format!("Failed to lock pin1: {}", e))?;
p1.disconnect_from_pin(pin2);
}
// Disconnect pin2 from pin1
{
let mut p2 = pin2.lock();
let mut p2 = pin2
.lock()
.map_err(|e| format!("Failed to lock pin2: {}", e))?;
p2.disconnect_from_pin(pin1);
}
@ -138,7 +153,9 @@ impl ConnectionManager {
/// Disconnect all pins from a given pin
pub fn disconnect_all(&mut self, pin: &Arc<Mutex<Pin>>) -> Result<(), String> {
let pin_name = {
let p = pin.lock();
let p = pin
.lock()
.map_err(|e| format!("Failed to lock pin: {}", e))?;
p.name().to_string()
};
@ -165,7 +182,9 @@ impl ConnectionManager {
// Clear the pin's internal connections
{
let mut p = pin.lock();
let mut p = pin
.lock()
.map_err(|e| format!("Failed to lock pin: {}", e))?;
p.clear_connections();
}
@ -233,8 +252,8 @@ mod tests {
assert!(connect_pins(pin1.clone(), pin2.clone()).is_ok());
// Verify connection
let p1 = pin1.lock();
let p2 = pin2.lock();
let p1 = pin1.lock().unwrap();
let p2 = pin2.lock().unwrap();
assert_eq!(p1.get_connection_count(), 1);
assert_eq!(p2.get_connection_count(), 1);
@ -252,8 +271,8 @@ mod tests {
manager.disconnect_pins(&pin1, &pin2).unwrap();
let p1 = pin1.lock();
let p2 = pin2.lock();
let p1 = pin1.lock().unwrap();
let p2 = pin2.lock().unwrap();
assert_eq!(p1.get_connection_count(), 0);
assert_eq!(p2.get_connection_count(), 0);
@ -271,7 +290,7 @@ mod tests {
// Verify all pins are connected to each other
for i in 0..pins.len() {
let pin = pins[i].lock();
let pin = pins[i].lock().unwrap();
assert_eq!(pin.get_connection_count(), pins.len() - 1);
}
}
@ -288,7 +307,7 @@ mod tests {
manager.disconnect_all(&pin1).unwrap();
let p1 = pin1.lock();
let p1 = pin1.lock().unwrap();
assert_eq!(p1.get_connection_count(), 0);
}
}

325
src/gui/components.rs
View file

@ -48,11 +48,7 @@
//! - Recovery options are provided where applicable
use super::state::GuiState;
use crate::system_config::{ConfigurableSystem, SystemController};
use crate::virtual_clock::SimulationMode;
use eframe::egui;
use parking_lot::Mutex;
use std::sync::Arc;
/// Container for all GUI components
///
@ -76,8 +72,6 @@ use std::sync::Arc;
pub struct GuiComponents {
/// System control and management interface
control_panel: ControlPanel,
/// Timing/speed/mode/step controls
timing_controls: TimingControls,
/// RAM content inspection and visualization
memory_viewer: MemoryViewer,
/// ROM content inspection and visualization
@ -110,7 +104,6 @@ impl GuiComponents {
pub fn new() -> Self {
Self {
control_panel: ControlPanel::new(),
timing_controls: TimingControls::new(),
memory_viewer: MemoryViewer::new(),
rom_viewer: RomViewer::new(),
register_viewer: RegisterViewer::new(),
@ -127,31 +120,8 @@ impl GuiComponents {
/// # Arguments
/// * `ui` - egui UI context for rendering
/// * `state` - Mutable reference to GUI state for control operations
/// * `system` - Optional reference to the emulator system for actual control
pub fn render_control_panel(
&mut self,
ui: &mut egui::Ui,
state: &mut GuiState,
system: Option<&Arc<Mutex<ConfigurableSystem>>>,
) {
self.control_panel.render(ui, state, system);
}
/// Render the timing controls component
///
/// Displays simulation speed, mode, step controls, and virtual time.
///
/// # Arguments
/// * `ui` - egui UI context for rendering
/// * `state` - Mutable reference to GUI state for display and interaction
/// * `system` - Optional reference to the emulator system for clock control
pub fn render_timing_controls(
&mut self,
ui: &mut egui::Ui,
state: &mut GuiState,
system: Option<&Arc<Mutex<ConfigurableSystem>>>,
) {
self.timing_controls.render(ui, state, system);
pub fn render_control_panel(&mut self, ui: &mut egui::Ui, state: &mut GuiState) {
self.control_panel.render(ui, state);
}
/// Render the memory viewer component
@ -263,12 +233,7 @@ impl ControlPanel {
/// │ [Load ROM] [Start System] [Stop] [Reset] [Close] │
/// └─────────────────────────────────────────────────┘
/// ```
pub fn render(
&mut self,
ui: &mut egui::Ui,
state: &mut GuiState,
system: Option<&Arc<Mutex<ConfigurableSystem>>>,
) {
pub fn render(&mut self, ui: &mut egui::Ui, state: &mut GuiState) {
ui.horizontal(|ui| {
// Section header
ui.heading("System Control");
@ -282,28 +247,22 @@ impl ControlPanel {
// Start/Stop system button (context-sensitive)
if ui.button(&self.start_button_text).clicked() {
if !state.system_running {
self.start_system(state, system);
self.start_system(state);
}
}
// Stop system button (only enabled when running)
if ui.button("Stop System").clicked() && state.system_running {
self.stop_system(state, system);
self.stop_system(state);
}
// Reset system button
if ui.button("Reset System").clicked() {
self.reset_system(state, system);
self.reset_system(state);
}
// Application close button
if ui.button("Close").clicked() {
// Stop the system before closing if available
if let Some(sys) = system {
let mut sys_guard = sys.lock();
// Use the SystemController trait method explicitly
let _ = SystemController::stop(&mut *sys_guard);
}
// Close application - handled by eframe
ui.ctx().send_viewport_cmd(egui::ViewportCommand::Close);
}
@ -319,37 +278,12 @@ impl ControlPanel {
///
/// # Arguments
/// * `state` - Mutable reference to GUI state
/// * `system` - Optional reference to the emulator system
fn start_system(
&mut self,
state: &mut GuiState,
system: Option<&Arc<Mutex<ConfigurableSystem>>>,
) {
// Actually start the system if available
if let Some(sys) = system {
let mut sys_guard = sys.lock();
// Use the SystemController trait method explicitly
let result = SystemController::start(&mut *sys_guard);
match result {
Ok(()) => {
state.system_running = true;
self.start_button_text = "System Running...".to_string();
self.stop_button_enabled = true;
self.reset_button_enabled = true;
state.clear_error();
}
Err(e) => {
state.set_error(format!("Failed to start system: {}", e));
}
}
} else {
// No system available - just update UI state
state.system_running = true;
self.start_button_text = "System Running...".to_string();
self.stop_button_enabled = true;
self.reset_button_enabled = true;
state.clear_error();
}
fn start_system(&mut self, state: &mut GuiState) {
state.system_running = true;
self.start_button_text = "System Running...".to_string();
self.stop_button_enabled = true;
self.reset_button_enabled = true;
state.clear_error();
}
/// Stop the emulator system
@ -359,35 +293,11 @@ impl ControlPanel {
///
/// # Arguments
/// * `state` - Mutable reference to GUI state
/// * `system` - Optional reference to the emulator system
fn stop_system(
&mut self,
state: &mut GuiState,
system: Option<&Arc<Mutex<ConfigurableSystem>>>,
) {
// Actually stop the system if available
if let Some(sys) = system {
let mut sys_guard = sys.lock();
// Use the SystemController trait method explicitly
let result = SystemController::stop(&mut *sys_guard);
match result {
Ok(()) => {
state.system_running = false;
self.start_button_text = "Start System".to_string();
self.stop_button_enabled = false;
state.clear_error();
}
Err(e) => {
state.set_error(format!("Failed to stop system: {}", e));
}
}
} else {
// No system available - just update UI state
state.system_running = false;
self.start_button_text = "Start System".to_string();
self.stop_button_enabled = false;
state.clear_error();
}
fn stop_system(&mut self, state: &mut GuiState) {
state.system_running = false;
self.start_button_text = "Start System".to_string();
self.stop_button_enabled = false;
state.clear_error();
}
/// Reset the emulator system
@ -397,19 +307,7 @@ impl ControlPanel {
///
/// # Arguments
/// * `state` - Mutable reference to GUI state
/// * `system` - Optional reference to the emulator system
fn reset_system(
&mut self,
state: &mut GuiState,
system: Option<&Arc<Mutex<ConfigurableSystem>>>,
) {
// Stop the system first if available
if let Some(sys) = system {
let mut sys_guard = sys.lock();
// Use the SystemController trait method explicitly
let _ = SystemController::stop(&mut *sys_guard);
}
// Reset UI state
fn reset_system(&mut self, state: &mut GuiState) {
state.system_running = false;
state.cycle_count = 0;
self.start_button_text = "Start System".to_string();
@ -419,191 +317,6 @@ impl ControlPanel {
}
}
/// Timing controls component for simulation speed, mode, and step management.
///
/// This component provides controls for the virtual clock system:
/// - **Speed slider**: Logarithmic scale from 0.001× to 100×
/// - **Mode selector**: RealTime / MaxSpeed / SingleStep radio buttons
/// - **Step button**: Advance one tick in SingleStep mode
/// - **Virtual time display**: Current time, tick count, actual vs target speed
///
/// ## Logarithmic Slider Mapping
///
/// The slider position `t` (0.0 to 1.0) maps to speed via:
/// `speed = 10^(t * 5 - 3)` giving range [0.001, 100.0]
pub struct TimingControls {
/// Current slider position (0.0 to 1.0), mapped logarithmically to speed
speed_slider_pos: f32,
}
impl TimingControls {
/// Create a new timing controls component
pub fn new() -> Self {
// Default: 1.0x speed → log10(1.0) = 0, so t = (0 + 3) / 5 = 0.6
Self {
speed_slider_pos: 0.6,
}
}
/// Convert slider position (0..1) to speed multiplier using logarithmic scale.
///
/// Range: 0.001× (position 0.0) to 100.0× (position 1.0)
/// Formula: speed = 10^(pos * 5 - 3)
fn pos_to_speed(pos: f32) -> f64 {
let pos = pos.clamp(0.0, 1.0) as f64;
10f64.powf(pos * 5.0 - 3.0)
}
/// Convert speed multiplier to slider position (0..1) using logarithmic scale.
///
/// Formula: pos = (log10(speed) + 3) / 5
fn speed_to_pos(speed: f64) -> f32 {
if speed <= 0.0 {
return 0.0;
}
let pos = (speed.log10() + 3.0) / 5.0;
pos.clamp(0.0, 1.0) as f32
}
/// Render the timing controls interface.
///
/// # Layout
/// ```text
/// ┌──────────────────────────────────────────────────────────────────┐
/// │ Timing Controls │
/// │ Speed: [========●===========] 1.00× (actual: 0.98×) │
/// │ Mode: (●) RealTime ( ) MaxSpeed ( ) SingleStep [Step] │
/// │ Virtual Time: 1.23 ms | Ticks: 3,690 | Paused: No │
/// └──────────────────────────────────────────────────────────────────┘
/// ```
pub fn render(
&mut self,
ui: &mut egui::Ui,
state: &mut GuiState,
system: Option<&Arc<Mutex<ConfigurableSystem>>>,
) {
// Sync slider position from actual clock speed so external changes
// (e.g., console "speed 0.1" command) are reflected in the GUI.
self.speed_slider_pos = Self::speed_to_pos(state.timing_state.target_speed);
ui.vertical(|ui| {
ui.heading("Timing Controls");
// Speed slider row
ui.horizontal(|ui| {
ui.label("Speed:");
let slider = egui::Slider::new(&mut self.speed_slider_pos, 0.0..=1.0)
.show_value(false)
.step_by(0.001);
let response = ui.add(slider);
if response.changed() {
let new_speed = Self::pos_to_speed(self.speed_slider_pos);
if let Some(sys) = system {
let sys_guard = sys.lock();
let clock = sys_guard.get_virtual_clock();
clock.set_speed_multiplier(new_speed);
// If in MaxSpeed mode, switch back to RealTime when slider moves
if clock.mode() == SimulationMode::MaxSpeed {
clock.set_mode(SimulationMode::RealTime);
}
}
}
// Show current target speed
let speed_text = state.timing_state.format_speed();
ui.label(format!("Target: {}", speed_text));
// Show actual speed
let actual_text = state.timing_state.format_actual_speed();
ui.label(format!("Actual: {}", actual_text));
});
// Mode selector and step button row
ui.horizontal(|ui| {
ui.label("Mode:");
let current_mode = state.timing_state.mode.as_str();
let is_realtime = current_mode == "RealTime";
let is_maxspeed = current_mode == "MaxSpeed";
let is_singlestep = current_mode == "SingleStep";
// RealTime radio
if ui.radio(is_realtime, "RealTime").clicked() {
self.apply_mode(system, SimulationMode::RealTime);
}
// MaxSpeed radio
if ui.radio(is_maxspeed, "MaxSpeed").clicked() {
self.apply_mode(system, SimulationMode::MaxSpeed);
}
// SingleStep radio
if ui.radio(is_singlestep, "SingleStep").clicked() {
self.apply_mode(system, SimulationMode::SingleStep);
}
ui.separator();
// Step button (enabled only in SingleStep mode)
let step_pending = state.timing_state.step_pending;
let step_button = ui.add_enabled(
is_singlestep && !step_pending,
egui::Button::new("Step"),
);
if step_button.clicked() {
if let Some(sys) = system {
let sys_guard = sys.lock();
let clock = sys_guard.get_virtual_clock();
clock.trigger_step();
}
}
if is_singlestep && step_pending {
ui.colored_label(egui::Color32::YELLOW, "⏳ Step pending...");
}
});
// Virtual time display row
ui.horizontal(|ui| {
ui.label("Virtual Time:");
ui.strong(state.timing_state.format_virtual_time());
ui.separator();
ui.label("Ticks:");
ui.strong(format!("{}", state.timing_state.tick_count));
ui.separator();
// Paused indicator
if state.timing_state.paused {
ui.colored_label(egui::Color32::YELLOW, "⏸ Paused");
} else if state.system_running {
ui.colored_label(egui::Color32::GREEN, "▶ Running");
} else {
ui.colored_label(egui::Color32::RED, "⏹ Stopped");
}
});
});
ui.separator();
}
/// Apply a simulation mode change to the virtual clock.
fn apply_mode(
&mut self,
system: Option<&Arc<Mutex<ConfigurableSystem>>>,
mode: SimulationMode,
) {
if let Some(sys) = system {
let sys_guard = sys.lock();
let clock = sys_guard.get_virtual_clock();
clock.set_mode(mode);
}
}
}
/// Memory viewer component for displaying RAM contents and state
///
/// The memory viewer provides comprehensive RAM inspection capabilities,
@ -1072,7 +785,7 @@ impl RomLoader {
}
// Display currently selected file
if let Some(ref file) = self.selected_file {
if let Some(ref file) = self.selected_file.clone() {
ui.label(format!("Selected: {}", file));
}

886
src/gui/console.rs
View file

File diff suppressed because it is too large Load diff

32
src/gui/mod.rs
View file

@ -9,8 +9,7 @@ pub mod state;
use crate::system_config::ConfigurableSystem;
use eframe::egui;
use parking_lot::Mutex;
use std::sync::Arc;
use std::sync::{Arc, Mutex};
/// Main GUI application structure
///
@ -94,8 +93,7 @@ impl GuiApp {
///
/// # Example
/// ```rust,no_run
/// use parking_lot::Mutex;
/// use std::sync::Arc;
/// use std::sync::{Arc, Mutex};
/// use rusty_emu::gui::GuiApp;
/// use rusty_emu::system_config::SystemFactory;
///
@ -150,8 +148,9 @@ impl eframe::App for GuiApp {
if ctrl_q_pressed {
// Stop the system if available
if let Some(system) = self.get_system() {
let mut sys = system.lock();
sys.stop();
if let Ok(mut sys) = system.lock() {
sys.stop();
}
}
// Close the GUI window
ctx.send_viewport_cmd(egui::ViewportCommand::Close);
@ -193,23 +192,9 @@ impl GuiApp {
// Main GUI sections - organized for optimal workflow
self.components
.render_control_panel(ui, &mut self.gui_state, self.system.as_ref());
// Timing controls: speed slider, mode selector, step button, time display
.render_control_panel(ui, &mut self.gui_state);
self.components
.render_timing_controls(ui, &mut self.gui_state, self.system.as_ref());
// Memory section: RAM and ROM side by side
ui.horizontal(|ui| {
ui.vertical(|ui| {
self.components
.render_memory_viewer(ui, &mut self.gui_state);
});
ui.vertical(|ui| {
self.components.render_rom_viewer(ui, &mut self.gui_state);
});
});
.render_memory_viewer(ui, &mut self.gui_state);
self.components
.render_register_viewer(ui, &mut self.gui_state);
self.components.render_status_bar(ui, &self.gui_state);
@ -237,8 +222,7 @@ impl GuiApp {
///
/// # Example
/// ```rust,no_run
/// use parking_lot::Mutex;
/// use std::sync::Arc;
/// use std::sync::{Arc, Mutex};
/// use rusty_emu::gui::run_gui;
/// use rusty_emu::system_config::SystemFactory;
///

225
src/gui/state.rs
View file

@ -5,11 +5,7 @@
//! to emulator state for real-time GUI updates.
use crate::system_config::ConfigurableSystem;
use crate::real_time_governor::RealTimeGovernor;
use crate::virtual_clock::SimulationMode;
use parking_lot::Mutex;
use std::sync::Arc;
use std::time::Duration;
use std::sync::{Arc, Mutex};
/// GUI state structure containing all UI-relevant data
#[derive(Debug, Clone)]
@ -32,104 +28,6 @@ pub struct GuiState {
pub register_state: RegisterState,
/// Last error message
pub last_error: Option<String>,
/// Timing/speed control state
pub timing_state: SimulationTimingState,
/// Speed snapshot for measuring actual simulation speed.
/// Uses RealTimeGovernor::SpeedSnapshot which wraps (Instant, u64) properly.
speed_snap_prev: Option<crate::real_time_governor::SpeedSnapshot>,
}
/// Timing and speed control state for the simulation.
///
/// Named `SimulationTimingState` to avoid confusion with the hardware
/// [`TimingState`](crate::components::common::intel_400x::TimingState) enum
/// that represents component-level timing states (e.g., WaitLatency, DriveData).
#[derive(Debug, Clone)]
pub struct SimulationTimingState {
/// Current virtual time in nanoseconds
pub virtual_time_ns: u64,
/// Total ticks elapsed
pub tick_count: u64,
/// Current target speed multiplier (from VirtualClock)
pub target_speed: f64,
/// Actual measured speed ratio (from RealTimeGovernor snapshots)
/// 1.0 = real-time, 0.5 = half speed, 2.0 = double speed
pub actual_speed: f64,
/// Current simulation mode as string: "RealTime", "MaxSpeed", "SingleStep"
pub mode: String,
/// Whether a step is pending (SingleStep mode)
pub step_pending: bool,
/// Whether the simulation is paused
pub paused: bool,
}
impl Default for SimulationTimingState {
fn default() -> Self {
Self {
virtual_time_ns: 0,
tick_count: 0,
target_speed: 1.0,
actual_speed: 0.0,
mode: "RealTime".to_string(),
step_pending: false,
paused: false,
}
}
}
/// Format a virtual time value in nanoseconds as a human-readable string.
///
/// Automatically selects the most appropriate unit (ns, µs, ms, s).
/// This is the single source of truth for virtual time formatting,
/// used by both the GUI and console interfaces.
pub fn format_virtual_time_ns(ns: u64) -> String {
if ns == 0 {
return "0 ns".to_string();
}
if ns < 1_000 {
format!("{} ns", ns)
} else if ns < 1_000_000 {
format!("{:.2} µs", ns as f64 / 1_000.0)
} else if ns < 1_000_000_000 {
format!("{:.2} ms", ns as f64 / 1_000_000.0)
} else {
format!("{:.3} s", ns as f64 / 1_000_000_000.0)
}
}
impl SimulationTimingState {
/// Format virtual time as a human-readable string.
///
/// Automatically selects the most appropriate unit (ns, µs, ms, s).
/// Delegates to [`format_virtual_time_ns`] for the actual formatting.
pub fn format_virtual_time(&self) -> String {
format_virtual_time_ns(self.virtual_time_ns)
}
/// Format the speed multiplier for display.
pub fn format_speed(&self) -> String {
if self.target_speed >= 100.0 {
format!("{:.0}×", self.target_speed)
} else if self.target_speed >= 1.0 {
format!("{:.1}×", self.target_speed)
} else {
format!("{:.3}×", self.target_speed)
}
}
/// Format the actual measured speed for display.
pub fn format_actual_speed(&self) -> String {
let speed = self.actual_speed;
if speed <= 0.0 {
"—".to_string()
} else if speed >= 100.0 {
format!("{:.0}×", speed)
} else if speed >= 1.0 {
format!("{:.1}×", speed)
} else {
format!("{:.3}×", speed)
}
}
}
/// System information for display
@ -219,65 +117,66 @@ impl GuiState {
selected_register: 0,
},
last_error: None,
timing_state: SimulationTimingState::default(),
speed_snap_prev: None,
}
}
/// Update state from the current system
pub fn update_from_system(&mut self, system: &Arc<Mutex<ConfigurableSystem>>) {
let system_guard = system.lock();
// Update basic system state
self.system_running = system_guard.is_running();
if let Ok(system_guard) = system.lock() {
// Update basic system state
self.system_running = system_guard.is_running();
// Update system info if not already set
if self.system_info.is_none() {
self.system_info = Some(system_guard.get_system_info().into());
}
// Update system info if not already set
if self.system_info.is_none() {
self.system_info = Some(system_guard.get_system_info().into());
}
// Update component states
self.update_component_states(&system_guard);
// Update component states
self.update_component_states(&system_guard);
// Update CPU register state from real data
self.update_register_state(&system_guard);
// Update CPU register state from real data
self.update_register_state(&system_guard);
// Update RAM state from real data
self.update_ram_state(&system_guard);
// Update RAM state from real data
self.update_ram_state(&system_guard);
// Update ROM state from real data
self.update_rom_state(&system_guard);
// Update ROM state from real data
self.update_rom_state(&system_guard);
// Update timing state from virtual clock
self.update_timing_state(&system_guard);
// Update cycle count (simulate for now)
if self.system_running {
self.cycle_count += 1;
// Update cycle count (simulate for now)
if self.system_running {
self.cycle_count += 1;
}
}
}
/// Update component running states
/// Uses blocking locks for consistent GUI data - GUI can wait for simulation
/// Uses try_lock() to avoid potential deadlocks when multiple threads
/// access components in different orders
fn update_component_states(&mut self, system: &ConfigurableSystem) {
let components = system.get_components();
// Use blocking locks for consistent data - GUI can wait for simulation
self.component_states.cpu_running = components
.get("CPU_4004")
.map_or(false, |comp| comp.lock().is_running());
// Use try_lock() to avoid blocking - if we can't get the lock immediately,
// just assume the component is not running (safe default for GUI display)
self.component_states.cpu_running = components.get("CPU_4004").map_or(false, |comp| {
comp.try_lock().map_or(false, |c| c.is_running())
});
self.component_states.ram_running = components
.get("RAM_4002")
.map_or(false, |comp| comp.lock().is_running());
self.component_states.ram_running = components.get("RAM_4002").map_or(false, |comp| {
comp.try_lock().map_or(false, |c| c.is_running())
});
self.component_states.rom_running = components
.get("ROM_4001_1")
.or_else(|| components.get("ROM_4001_2"))
.map_or(false, |comp| comp.lock().is_running());
.map_or(false, |comp| {
comp.try_lock().map_or(false, |c| c.is_running())
});
self.component_states.clock_running = components
.get("SYSTEM_CLOCK")
.map_or(false, |comp| comp.lock().is_running());
self.component_states.clock_running =
components.get("SYSTEM_CLOCK").map_or(false, |comp| {
comp.try_lock().map_or(false, |c| c.is_running())
});
}
/// Update CPU register state from real component data
@ -324,56 +223,6 @@ impl GuiState {
}
}
/// Update timing state from the virtual clock
fn update_timing_state(&mut self, system: &ConfigurableSystem) {
let clock = system.get_virtual_clock();
// Read current values from the virtual clock
self.timing_state.virtual_time_ns = clock.now_ns();
self.timing_state.tick_count = clock.tick_count();
self.timing_state.target_speed = clock.speed_multiplier();
self.timing_state.step_pending = clock.is_step_pending();
self.timing_state.paused = clock.is_paused();
let mode = clock.mode();
self.timing_state.mode = match mode {
SimulationMode::RealTime => "RealTime".to_string(),
SimulationMode::MaxSpeed => "MaxSpeed".to_string(),
SimulationMode::SingleStep => "SingleStep".to_string(),
};
// Compute actual speed using RealTimeGovernor's snapshot infrastructure.
// Shift current → previous, take new measurement, then compute delta.
// This avoids the precision loss from accumulating nanos in a single u128
// and delegates the calculation to the well-tested compute_speed() method.
//
// We require at least 100ms of wall-clock time between snapshots to produce
// a stable measurement. At 60 FPS, consecutive frames are ~16ms apart, which
// is too short for accurate speed calculation — especially at low simulation
// speeds where virtual time barely advances between frames.
const MIN_SPEED_SAMPLE_INTERVAL: Duration = Duration::from_millis(100);
let new_snap = RealTimeGovernor::take_speed_snapshot(clock);
let should_compute = self.speed_snap_prev.as_ref().map_or(false, |prev| {
new_snap.wall.duration_since(prev.wall) >= MIN_SPEED_SAMPLE_INTERVAL
});
if should_compute {
if let Some(prev) = &self.speed_snap_prev {
let speed = RealTimeGovernor::compute_speed(prev, &new_snap);
if speed > 0.0 {
self.timing_state.actual_speed = speed;
}
}
// Only shift snapshots when we actually computed a new speed value,
// so the next computation uses a baseline at least 100ms old.
self.speed_snap_prev = Some(new_snap);
} else if self.speed_snap_prev.is_none() {
// First frame — initialize the baseline snapshot
self.speed_snap_prev = Some(new_snap);
}
}
/// Set an error message
pub fn set_error(&mut self, error: String) {
self.last_error = Some(error);

3
src/lib.rs
View file

@ -11,14 +11,11 @@
pub mod component;
pub mod components;
pub mod component_timing;
pub mod connection;
pub mod gui;
pub mod pin;
pub mod real_time_governor;
pub mod system_config;
pub mod types;
pub mod virtual_clock;
// Re-export commonly used items for easier importing
pub use component::{BaseComponent, Component};

180
src/main.rs
View file

@ -68,14 +68,13 @@
//! cargo run -- --help
//! ```
use parking_lot::Mutex;
use rusty_emu::gui::console::{run_console, ConsoleConfig};
use rusty_emu::gui::run_gui;
use rusty_emu::system_config::{ConfigurableSystem, SystemFactory};
use std::env;
use std::fs;
use std::process;
use std::sync::Arc;
use std::sync::{Arc, Mutex};
use std::thread;
use std::time::{Duration, Instant};
@ -207,16 +206,15 @@ fn main() {
"Console features: Real-time monitoring, formatted output, non-blocking operation"
);
// Start the emulator system using start() which doesn't block
// This allows the console interface to access the system while emulation runs
{
let mut system = system_arc.lock();
println!("DEBUG: Starting system for console mode (non-blocking)");
if let Err(e) = system.start() {
eprintln!("Failed to start system: {}", e);
process::exit(1);
// Start the emulator system in a separate thread
// This allows the console interface to run while emulation continues
let system_runner = system_arc.clone();
thread::spawn(move || {
if let Ok(mut system) = system_runner.lock() {
println!("DEBUG: Starting system for console mode");
system.run();
}
}
});
// Launch console interface (blocks until console is closed)
if let Err(e) = run_console(system_arc, console_config) {
@ -231,16 +229,15 @@ fn main() {
println!("Starting graphical user interface...");
println!("GUI features: Visual monitoring, interactive controls, real-time updates");
// Start the emulator system using start() which doesn't block
// Start the emulator system in a separate thread
// This allows the GUI to remain responsive while emulation runs
{
let mut system = system_arc.lock();
println!("DEBUG: Starting system for GUI mode (non-blocking)");
if let Err(e) = system.start() {
eprintln!("Failed to start system: {}", e);
process::exit(1);
let system_runner = system_arc.clone();
thread::spawn(move || {
if let Ok(mut system) = system_runner.lock() {
println!("DEBUG: Starting system for GUI mode");
system.run();
}
}
});
// Launch GUI application (blocks until GUI window is closed)
// The GUI will handle all user interactions and system monitoring
@ -387,47 +384,32 @@ fn load_program_data(filename: &str) -> Result<Vec<u8>, String> {
fn get_default_fibonacci_program() -> Vec<u8> {
// Fibonacci program for Intel 4004
// Computes Fibonacci numbers using registers R0-R3 and writes to RAM.
//
// Register usage:
// R0 = F(n-2) (two steps back)
// R1 = F(n-1) (one step back)
// R2 = loop counter (counts up, exit when ISZ wraps to 0)
// R3 = temp for register rotation
//
// Opcode reference (per Intel 4004 datasheet):
// FIM Rp,data = 0x20+2*Rp, data (load register pair immediate, 2-byte)
// LD R = 0xA0+R (load register R into ACC)
// XCH R = 0xB0+R (exchange ACC ↔ register R)
// ADD R = 0x80+R (ACC = ACC + R + Carry)
// CLB = 0xF0 (clear both ACC and Carry)
// WRM = 0xE0 (write ACC to RAM at current pointer)
// ISZ R,addr = 0x70+R, addr (increment R; jump to addr if R ≠ 0, 2-byte)
// This implements a simple Fibonacci sequence generator
vec![
// === Address 0x00: Initialize registers ===
0x20, 0x01, // FIM R0/R1, 0x01 → R0=0, R1=1 (F(0)=0, F(1)=1)
0x22, 0x78, // FIM R2/R3, 0x78 → R2=7 (loop counter, ISZ wraps 7→8≠0→jumps, 8→9, ... 15→0→falls through = 8 iterations), R3=8
// === Address 0x04: Loop — compute F(n) = F(n-1) + F(n-2) ===
0xF0, // CLB (ACC=0, Carry=0)
0xA1, // LD R1 → ACC = F(n-1)
0x80, // ADD R0 → ACC = F(n-1) + F(n-2) + 0 = F(n)
0xE0, // WRM (write F(n) to RAM)
// === Address 0x08: Rotate registers: R0 ← R1, R1 ← F(n) ===
// F(n) is still in ACC after WRM (WRM doesn't change ACC)
0xB3, // XCH R3 → ACC = old R3, R3 = F(n)
0xA1, // LD R1 → ACC = F(n-1)
0xB0, // XCH R0 → ACC = old F(n-2), R0 = F(n-1)
0xA3, // LD R3 → ACC = F(n)
0xB1, // XCH R1 → ACC = old F(n-1), R1 = F(n)
// === Address 0x0E: Loop control ===
0x72, 0x04, // ISZ R2, 0x04 → R2++; if R2 ≠ 0 jump to 0x04 (loop)
// === Address 0x10: Exit ===
0x00, // NOP (halt placeholder)
0x00, // NOP (halt placeholder)
0x20, 0x00, // LDM 0 (Load accumulator with 0) - First Fibonacci number
0x10, 0x00, // LD 0 (Load accumulator from register 0)
0x50, // WRM (Write accumulator to RAM at current pointer)
0x21, 0x01, // LDM 1 (Load accumulator with 1) - Second Fibonacci number
0x10, 0x01, // LD 1 (Load accumulator from register 1)
0x50, // WRM (Write accumulator to RAM)
// Fibonacci calculation loop
0x00, 0x02, // LD 2 (Load register 2 into accumulator) - Loop counter
0x76, // IAC (Increment accumulator)
0x00, 0x02, // LD 2 (Store back to register 2)
// Calculate next Fibonacci number: F(n) = F(n-1) + F(n-2)
0x00, 0x00, // LD 0 (Load F(n-2) into accumulator)
0x10, 0x01, // ADD 1 (Add F(n-1) to accumulator)
0x50, // WRM (Store result to RAM)
// Update registers for next iteration
0x00, 0x01, // LD 1 (Load F(n-1) into accumulator)
0x00, 0x00, // LD 0 (Store F(n-1) to register 0)
0x50, // WRM (Write to RAM - this will be read back as F(n-2))
// Check if we've calculated enough numbers (8 iterations)
0x00, 0x02, // LD 2 (Load loop counter)
0x30, 0x08, // JCN 8 (Jump if accumulator == 8) - Exit condition
0x40, 0x0C, // JCN 12 (Jump back to loop start)
// Exit - halt program
0x00, 0x00, // NOP (placeholder for halt)
]
}
@ -483,12 +465,13 @@ fn run_system_demo(system: ConfigurableSystem) {
println!("CPU Speed: {} Hz", info.cpu_speed);
// Run system in a separate thread
let system_arc = Arc::new(Mutex::new(system));
let system_arc = std::sync::Arc::new(std::sync::Mutex::new(system));
let system_clone = system_arc.clone();
let handle = thread::spawn(move || {
let mut system = system_clone.lock();
system.run();
if let Ok(mut system) = system_clone.lock() {
system.run();
}
});
// Start monitoring in a separate thread
@ -510,18 +493,16 @@ fn run_system_demo(system: ConfigurableSystem) {
// Check for timeout
if start_time.elapsed() >= timeout {
println!("\nSimulation timed out after 10 seconds - stopping system");
{
let mut system = system_arc.lock();
if let Ok(mut system) = system_arc.lock() {
system.stop();
}
*running.lock() = false;
*running.lock().unwrap() = false;
break;
}
{
let system = system_arc.lock();
if let Ok(system) = system_arc.lock() {
if !system.is_running() {
*running.lock() = false;
*running.lock().unwrap() = false;
break;
}
}
@ -554,8 +535,10 @@ fn monitor_system_state(system_arc: Arc<Mutex<ConfigurableSystem>>, running_arc:
thread::sleep(Duration::from_millis(100)); // Reasonable interval for console monitoring
// Check if we should still be running (fast check)
// parking_lot::Mutex::lock() returns MutexGuard directly (no Result)
let should_continue = *running_arc.lock();
let should_continue = match running_arc.lock() {
Ok(running_val) => *running_val,
Err(_) => true, // Continue if lock is poisoned
};
if !should_continue {
break;
@ -565,13 +548,12 @@ fn monitor_system_state(system_arc: Arc<Mutex<ConfigurableSystem>>, running_arc:
// High-frequency monitoring: try_lock for immediate availability
// This matches MCS-4's 11µs cycle timing without blocking emulation
// parking_lot::Mutex::try_lock() returns Option<MutexGuard>
match system_arc.try_lock() {
Some(system) => {
Ok(system) => {
// Got the lock immediately - show detailed state (rare but possible)
display_detailed_system_state(&system, cycle);
}
None => {
Err(_) => {
// System is locked by emulation - this is normal and expected
// Show basic state without trying to acquire locks
display_basic_system_state(cycle);
@ -597,43 +579,45 @@ fn display_detailed_system_state(system: &ConfigurableSystem, cycle: u32) {
// CPU State Section
if let Some(cpu_component) = system.get_components().get("CPU_4004") {
let cpu = cpu_component.lock();
println!("│ CPU STATE: │");
println!(
"│ Status: {} │",
if cpu.is_running() {
"Running"
} else {
"Stopped"
}
);
println!(
"│ Component: {} │",
cpu.name()
);
if let Ok(cpu) = cpu_component.lock() {
println!("│ CPU STATE: │");
println!(
"│ Status: {} │",
if cpu.is_running() {
"Running"
} else {
"Stopped"
}
);
println!(
"│ Component: {} │",
cpu.name()
);
}
} else {
println!("│ CPU_4004 component not found │");
}
// RAM Section
if let Some(ram_component) = system.get_components().get("RAM_4002") {
let ram = ram_component.lock();
println!(
"│ RAM_4002: {} ({}) │",
ram.name(),
if ram.is_running() {
"Running"
} else {
"Stopped"
}
);
if let Ok(ram) = ram_component.lock() {
println!(
"│ RAM_4002: {} ({}) │",
ram.name(),
if ram.is_running() {
"Running"
} else {
"Stopped"
}
);
}
}
// Component Status Summary
let running_count = system
.get_components()
.values()
.filter(|comp| comp.lock().is_running())
.filter(|comp| comp.lock().map_or(false, |c| c.is_running()))
.count();
println!("│ │");
println!(

76
src/pin.rs
View file

@ -1,7 +1,6 @@
use parking_lot::Mutex;
use std::cmp::Ordering;
use std::collections::HashMap;
use std::sync::Arc;
use std::sync::{Arc, Mutex};
use std::time::{Duration, Instant};
#[derive(Debug, Clone, Copy, PartialEq)]
@ -113,59 +112,6 @@ impl Pin {
self.recalculate_value();
}
/// Set a driver on this pin without triggering propagation to connected pins.
/// This is used during propagation to avoid deadlocks with bidirectional connections.
fn set_driver_no_propagate(
&mut self,
driver_name: String,
value: PinValue,
strength: DriveStrength,
) {
if value == PinValue::HighZ && strength == DriveStrength::HighImpedance {
self.drivers.remove(&driver_name);
} else {
self.drivers.insert(driver_name, (value, strength));
}
self.last_update = Instant::now();
// Recalculate value locally but do NOT propagate
self.recalculate_value_no_propagate();
}
/// Recalculate the settled value from current drivers without propagating.
fn recalculate_value_no_propagate(&mut self) {
if self.drivers.is_empty() {
self.settled_value = PinValue::HighZ;
return;
}
let mut max_strength = DriveStrength::HighImpedance;
for (_, strength) in self.drivers.values() {
if *strength > max_strength {
max_strength = *strength;
}
}
if max_strength == DriveStrength::HighImpedance {
self.settled_value = PinValue::HighZ;
return;
}
let strong_drivers: Vec<PinValue> = self
.drivers
.values()
.filter(|(_, strength)| *strength == max_strength)
.map(|(value, _)| *value)
.collect();
if strong_drivers.iter().any(|v| *v == PinValue::Low) {
self.settled_value = PinValue::Low;
} else if strong_drivers.iter().any(|v| *v == PinValue::High) {
self.settled_value = PinValue::High;
} else {
self.settled_value = PinValue::HighZ;
}
}
pub fn remove_driver(&mut self, driver_name: &str) {
self.drivers.remove(driver_name);
self.last_update = Instant::now();
@ -242,13 +188,11 @@ impl Pin {
};
for connected_pin in &self.connected_pins {
let mut pin = connected_pin.lock();
// Copy all our drivers with their strengths using the no-propagate
// variant to avoid deadlock with bidirectional connections.
// When Pin A propagates to Pin B, Pin B must not propagate back
// to Pin A (which is still locked by this thread).
for (driver_name, (value, strength)) in &self.drivers {
pin.set_driver_no_propagate(driver_name.clone(), *value, *strength);
if let Ok(mut pin) = connected_pin.lock() {
// Copy all our drivers with their strengths
for (driver_name, (value, strength)) in &self.drivers {
pin.set_driver_with_strength(Some(driver_name.clone()), *value, *strength);
}
}
}
@ -359,6 +303,8 @@ impl std::fmt::Display for Pin {
#[cfg(test)]
mod tests {
use super::*;
use std::sync::Arc;
use std::sync::Mutex;
#[test]
fn test_pin_creation() {
@ -413,13 +359,13 @@ mod tests {
// Connect pins
{
let mut p1 = pin1.lock();
let mut p1 = pin1.lock().unwrap();
p1.connect_to(pin2.clone());
}
// Drive pin1
{
let mut p1 = pin1.lock();
let mut p1 = pin1.lock().unwrap();
p1.set_driver(Some("test".to_string()), PinValue::High);
}
@ -427,7 +373,7 @@ mod tests {
std::thread::sleep(Duration::from_millis(1));
// Check pin2
let p2 = pin2.lock();
let p2 = pin2.lock().unwrap();
assert_eq!(p2.read(), PinValue::High);
}

387
src/real_time_governor.rs
View file

@ -1,387 +0,0 @@
//! Real-Time Governor for controlling virtual clock advancement.
//!
//! The `RealTimeGovernor` runs in its own thread and is responsible for advancing
//! the `VirtualClock` at the appropriate rate. It maps virtual time to wall-clock
//! time based on the speed multiplier, similar to how UAE and VICE synchronize
//! at frame boundaries.
//!
//! # Modes
//!
//! - **RealTime**: Advances virtual time and sleeps to match wall-clock × speed_multiplier.
//! At 1.0×, one virtual nanosecond maps to one wall-clock nanosecond.
//! At 0.1×, one virtual nanosecond takes 10 wall-clock nanoseconds.
//!
//! - **MaxSpeed**: Advances virtual time as fast as the host CPU allows.
//! No sleeping — pure computation speed. Useful for testing and fast-forwarding.
//!
//! - **SingleStep**: Advances virtual time by one tick only when the user triggers it.
//! Useful for debugging individual clock phases or instruction cycles.
use std::sync::Arc;
use std::thread;
use std::time::{Duration, Instant};
use crate::virtual_clock::{SimulationMode, VirtualClock};
/// Minimum practical speed multiplier for real-time mode.
///
/// Values below this produce wall-clock sleep durations so large that the
/// simulation effectively freezes. The same constant should be used in
/// `VirtualClock::set_speed_multiplier()` to reject impractical values early.
const MIN_SPEED_MULTIPLIER: f64 = 0.0001; // 10,000× slower than real-time
/// Governor that controls the rate of virtual time advancement.
///
/// Runs in its own thread, continuously advancing the shared `VirtualClock`
/// based on the current simulation mode and speed multiplier.
pub struct RealTimeGovernor {
/// Shared virtual clock to advance.
clock: Arc<VirtualClock>,
/// Number of ticks to batch before checking wall-clock time.
/// Higher values = less overhead but coarser synchronization.
/// At 333ns/tick, a batch of 100 = 33.3µs per sync point.
batch_size: u32,
}
impl Drop for RealTimeGovernor {
fn drop(&mut self) {
// Ensure component threads are unblocked if the governor panics
// or is dropped unexpectedly. stop() is idempotent — safe to call
// even if already stopped.
self.clock.stop();
}
}
impl RealTimeGovernor {
/// Create a new RealTimeGovernor.
///
/// # Parameters
/// - `clock`: Shared virtual clock to advance. Tick size is read dynamically
/// from the clock via `clock.tick_size_ns()`, so live changes are respected.
/// - `batch_size`: Number of ticks to batch between wall-clock sync points.
/// Default: 100 (good balance between overhead and synchronization accuracy).
pub fn new(clock: Arc<VirtualClock>, batch_size: u32) -> Self {
RealTimeGovernor {
clock,
batch_size: if batch_size == 0 { 100 } else { batch_size },
}
}
/// Create a governor with default batch size (100 ticks per sync).
pub fn with_defaults(clock: Arc<VirtualClock>) -> Self {
RealTimeGovernor::new(clock, 100)
}
/// Run the governor loop.
///
/// This method blocks until the virtual clock is stopped.
/// It should be called from its own thread:
///
/// ```rust,ignore
/// let governor = RealTimeGovernor::with_defaults(clock.clone());
/// let handle = thread::spawn(move || governor.run());
/// ```
///
/// # Lifecycle
///
/// **Note:** This method calls `clock.start()` automatically. You do not need
/// to call `clock.start()` yourself — it is idempotent, so doing so is safe
/// but unnecessary.
///
/// # Shutdown
///
/// The governor exits when `clock.stop()` is called. The governor itself
/// is consumed by this method (takes `self` by value) — all lifecycle
/// control (pause, resume, stop, mode changes) goes through the shared
/// `VirtualClock`. The governor cannot be reconfigured after `run()` is
/// called; create a new governor if different parameters are needed.
///
/// # Panic Safety
///
/// If this method panics before `clock.start()` is called (e.g., during initial setup),
/// component threads blocked in `VirtualClock::wait_for_start()` will deadlock because
/// no thread will ever call `stop()`. To prevent this, ensure `clock.stop()` is called
/// in any cleanup path (e.g., via `Drop` impl on the owning structure or a panic hook).
pub fn run(self) {
self.clock.start();
// Panic guard: ensure clock.stop() is called if the run loop panics,
// so component threads blocked in wait_for_start() / wait_until() are
// unblocked. Drop::drop also calls stop(), so this is a belt-and-
// suspenders approach — stop() is idempotent.
let clock_ref = &self.clock;
let result = std::panic::catch_unwind(std::panic::AssertUnwindSafe(|| {
loop {
if !clock_ref.is_running() {
break;
}
// Efficiently block (zero CPU) while paused instead of busy-polling.
// wait_for_resume() returns false if stopped while paused.
if !clock_ref.wait_for_resume() {
break;
}
match clock_ref.mode() {
SimulationMode::RealTime => self.run_realtime_batch(),
SimulationMode::MaxSpeed => self.run_maxspeed_batch(),
SimulationMode::SingleStep => self.run_single_step(),
}
}
}));
// Always stop the clock, even on panic.
clock_ref.stop();
if let Err(e) = result {
std::panic::resume_unwind(e);
}
}
/// RealTime mode: advance virtual time and sleep to match wall-clock.
///
/// Batches `batch_size` ticks, then sleeps to align virtual time
/// with wall-clock time × speed_multiplier.
fn run_realtime_batch(&self) {
// Read tick size from the clock to pick up live changes via set_tick_size()
let tick_ns = self.clock.tick_size_ns();
let speed_multiplier = self.clock.speed_multiplier().max(MIN_SPEED_MULTIPLIER);
// Reduce batch size at very slow speeds so pause/stop are honored promptly.
// At 0.001× speed with batch_size=100, each batch targets ~33ms of wall time,
// but at 0.0001× that balloons to 333ms — too long between pause checks.
let effective_batch = if speed_multiplier < 0.01 {
(self.batch_size as f64 * speed_multiplier / 0.01)
.max(1.0)
.ceil() as u32
} else {
self.batch_size
};
let batch_virtual_ns = tick_ns * effective_batch as u64;
// Calculate how long this batch should take in wall-clock time
// wall_time = virtual_time / speed_multiplier
// Use .max(1.0) to guard against underflow to 0 at extreme multipliers.
let target_wall_nanos = (batch_virtual_ns as f64 / speed_multiplier).max(1.0).round() as u64;
let target_wall = Duration::from_nanos(target_wall_nanos);
let start = Instant::now();
// Advance virtual time by effective_batch ticks
for _ in 0..effective_batch {
if !self.clock.is_running() || self.clock.is_paused() {
return;
}
self.clock.advance_one_tick();
}
let elapsed = start.elapsed();
// Sleep to match target wall-clock time
if elapsed < target_wall {
let sleep_duration = target_wall - elapsed;
thread::sleep(sleep_duration);
}
// If elapsed >= target_wall, we're running behind (CPU too slow)
// Just continue — the governor will report actual speed
}
/// MaxSpeed mode: advance virtual time as fast as possible.
///
/// Batches ticks and yields to other threads periodically.
fn run_maxspeed_batch(&self) {
for _ in 0..self.batch_size {
if !self.clock.is_running() || self.clock.is_paused() {
return;
}
self.clock.advance_one_tick();
}
// Yield to prevent starving component threads and GUI
thread::yield_now();
}
/// SingleStep mode: advance one tick when triggered by user.
fn run_single_step(&self) {
if self.clock.consume_step() {
self.clock.advance_one_tick();
} else {
// No step pending — sleep briefly to avoid busy-waiting
thread::sleep(Duration::from_micros(100));
}
}
/// Take a non-blocking snapshot of wall-clock and virtual time.
///
/// Take two snapshots spaced apart in time, then call
/// [`compute_speed`] to calculate the actual achieved speed multiplier.
/// This is safe to call from any thread, including the GUI thread.
///
/// # Example
///
/// ```rust,ignore
/// let snap1 = RealTimeGovernor::take_speed_snapshot(&clock);
/// // ... wait some time (e.g., next GUI frame) ...
/// let snap2 = RealTimeGovernor::take_speed_snapshot(&clock);
/// let actual_speed = RealTimeGovernor::compute_speed(&snap1, &snap2);
/// // Display: format!("Actual: {:.2}×", actual_speed)
/// ```
pub fn take_speed_snapshot(clock: &VirtualClock) -> SpeedSnapshot {
SpeedSnapshot {
wall: Instant::now(),
virtual_ns: clock.now_ns(),
}
}
/// Compute the actual speed multiplier from two snapshots.
///
/// Returns the ratio of virtual time elapsed to wall-clock time elapsed.
/// A value of 1.0 means real-time, 0.5 means half speed, 2.0 means double speed.
///
/// Returns 0.0 if the snapshots were taken too close together in wall-clock time
/// to produce a meaningful measurement.
pub fn compute_speed(before: &SpeedSnapshot, after: &SpeedSnapshot) -> f64 {
let wall_nanos = after.wall.duration_since(before.wall).as_nanos() as f64;
if wall_nanos == 0.0 {
return 0.0;
}
// Use saturating_sub to handle misordered snapshots gracefully (returns 0).
let virtual_delta = after.virtual_ns.saturating_sub(before.virtual_ns) as f64;
virtual_delta / wall_nanos
}
}
/// A point-in-time snapshot of wall-clock and virtual time, used for speed measurement.
///
/// See [`RealTimeGovernor::take_speed_snapshot`] and [`RealTimeGovernor::compute_speed`].
#[derive(Debug, Clone)]
pub struct SpeedSnapshot {
pub(crate) wall: Instant,
pub(crate) virtual_ns: u64,
}
#[cfg(test)]
mod tests {
use super::*;
#[test]
fn test_governor_maxspeed() {
let clock = Arc::new(VirtualClock::new(Duration::from_nanos(333)));
let governor = RealTimeGovernor::with_defaults(clock.clone());
// Run governor in background
let _clock_clone = Arc::clone(&clock);
let handle = thread::spawn(move || {
governor.run();
});
// Let it run for a bit
thread::sleep(Duration::from_millis(100));
// Virtual time should have advanced significantly
let vt = clock.now_ns();
assert!(vt > 0, "Virtual time should have advanced");
// Stop and wait for clean exit
clock.stop();
let _ = handle.join();
}
#[test]
fn test_governor_realtime_slow() {
let clock = Arc::new(VirtualClock::new(Duration::from_nanos(333)));
clock.set_speed_multiplier(0.001); // Very slow — easy to measure
let governor = RealTimeGovernor::new(
Arc::clone(&clock),
10, // Small batch for more frequent sync
);
let handle = thread::spawn(move || governor.run());
// Let it run for 100ms
thread::sleep(Duration::from_millis(100));
let vt = clock.now_ns();
// At 0.001x speed, 100ms wall time = 100µs virtual time
// With some tolerance for overhead
let expected_max = Duration::from_millis(100).as_nanos() as f64 * 0.001 * 2.0;
assert!(
(vt as f64) < expected_max,
"Virtual time should be much less than wall time at 0.001x speed. Got {}ns, expected < {}ns",
vt, expected_max
);
clock.stop();
let _ = handle.join();
}
#[test]
fn test_governor_single_step() {
let clock = Arc::new(VirtualClock::new(Duration::from_nanos(333)));
clock.set_mode(SimulationMode::SingleStep);
let governor = RealTimeGovernor::with_defaults(clock.clone());
let _clock_clone = Arc::clone(&clock);
let handle = thread::spawn(move || governor.run());
// Time should not advance without stepping
thread::sleep(Duration::from_millis(50));
assert_eq!(clock.now_ns(), 0, "Virtual time should not advance without stepping");
// Trigger a step
clock.trigger_step();
thread::sleep(Duration::from_millis(50));
assert_eq!(clock.now_ns(), 333, "Virtual time should advance by one tick after step");
// Trigger another step
clock.trigger_step();
thread::sleep(Duration::from_millis(50));
assert_eq!(clock.now_ns(), 666, "Virtual time should advance by another tick");
clock.stop();
let _ = handle.join();
}
#[test]
fn test_governor_pause_resume() {
let clock = Arc::new(VirtualClock::new(Duration::from_nanos(333)));
let governor = RealTimeGovernor::with_defaults(clock.clone());
let handle = thread::spawn(move || governor.run());
// Let it run
thread::sleep(Duration::from_millis(50));
let vt_before_pause = clock.now_ns();
assert!(vt_before_pause > 0);
// Pause
clock.pause();
thread::sleep(Duration::from_millis(50));
let vt_after_pause = clock.now_ns();
// Let it stay paused
thread::sleep(Duration::from_millis(50));
let vt_still_paused = clock.now_ns();
// Time should not have advanced significantly while paused
// (may advance by 1 tick due to race, but not more)
assert!(
vt_still_paused <= vt_after_pause + 1000,
"Virtual time should not advance while paused"
);
// Resume
clock.resume();
thread::sleep(Duration::from_millis(50));
let vt_after_resume = clock.now_ns();
assert!(
vt_after_resume > vt_still_paused,
"Virtual time should advance after resume"
);
clock.stop();
let _ = handle.join();
}
}

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src/system_config.rs
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src/virtual_clock.rs
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108
tests/README.md
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@ -15,17 +15,13 @@ timing, clock handling, and bus operations for Intel 400x series chips.
### Integration Tests (in tests/ directory)
1. **`lib.rs`** - Test library and common utilities
2. **`intel_400x_tests.rs`** - Tests for the common intel_400x functionality
3. **`intel_4001_state_machine_test.rs`** - Intel 4001 ROM state machine tests
4. **`intel_4002_state_machine_test.rs`** - Intel 4002 RAM state machine tests
5. **`intel_4003_state_machine_test.rs`** - Intel 4003 shift register state machine tests
6. **`intel_4004_state_machine_test.rs`** - Intel 4004 CPU state machine tests
7. **`integration_tests.rs`** - Integration tests with concrete chip implementations
8. **`json_integration_tests.rs`** - JSON system configuration integration tests
9. **`simple_test.rs`** - Working demonstration of core functionality
10. **`gui_tests.rs`** - GUI component tests
11. **`gui_integration_tests.rs`** - GUI integration tests
1. **`intel_400x_tests.rs`** - Tests for the common intel_400x functionality
2. **`mocks.rs`** - Mock implementations for testing hardware interactions
3. **`mock_based_tests.rs`** - Tests using mocks for data bus and pin operations
4. **`property_based_tests.rs`** - Property-based tests for state machine verification
5. **`integration_tests.rs`** - Integration tests with concrete chip implementations
6. **`working_test.rs`** - Working demonstration of core functionality
7. **`lib.rs`** - Test library and common utilities
### Test Categories
@ -38,37 +34,35 @@ timing, clock handling, and bus operations for Intel 400x series chips.
- **Data Bus Operations**: Test bit manipulation for 4-bit bus
- **Utility Functions**: Test helper functions and pin operations
#### 2. State Machine Tests (`intel_400x_state_machine_test.rs`)
#### 2. Mock-Based Tests (`mock_based_tests.rs`)
- **Intel 4001 ROM**: State machine transitions for ROM operations
- **Intel 4002 RAM**: State machine transitions for RAM operations
- **Intel 4003 Shift Register**: State machine transitions for shift register operations
- **Intel 4004 CPU**: State machine transitions for CPU instruction processing
- **Data Bus Operations**: Test read/write operations with controlled inputs
- **Clock Handling**: Test clock pin interactions and edge scenarios
- **Control Pins**: Test SYNC, CM, and RESET pin behavior
- **Timing State**: Test state machine with mock timing
- **Error Handling**: Test behavior with invalid inputs
#### 3. Integration Tests (`integration_tests.rs`)
#### 3. Property-Based Tests (`property_based_tests.rs`)
- **State Machine Invariants**: Verify state consistency properties
- **Type Conversions**: Test enum conversion roundtrips
- **Address Properties**: Test address assembly properties
- **Timing Properties**: Test duration and timing constraints
- **Concurrency Safety**: Test thread-safe behavior
#### 4. Integration Tests (`integration_tests.rs`)
- **Trait Implementation**: Verify concrete types implement traits correctly
- **Cross-Component Compatibility**: Test multiple components work together
- **Real Component Testing**: Test with actual Intel4001 implementation
- **Lifecycle Testing**: Test component initialization and cleanup
#### 4. JSON Configuration Tests (`json_integration_tests.rs`)
- **System Creation**: Test JSON-based system configuration loading
- **Component Wiring**: Verify automatic pin connections from config
- **Multiple Configurations**: Test basic, max, and I/O demo configurations
#### 5. Simple Tests (`simple_test.rs`)
#### 5. Working Tests (`working_test.rs`)
- **Core Functionality**: Demonstrates that the intel_400x module is testable
- **Basic Operations**: Tests fundamental features that work correctly
- **Regression Prevention**: Ensures core functionality remains stable
#### 6. GUI Tests (`gui_tests.rs`, `gui_integration_tests.rs`)
- **GUI Components**: Test GUI component rendering and state
- **GUI Integration**: Test GUI with full system integration
## Running the Tests
### Run All Tests
@ -80,23 +74,20 @@ cargo test
### Run Specific Test Categories
```bash
# Common functionality tests
# Unit tests only
cargo test intel_400x_tests
# State machine tests
cargo test intel_4001_state_machine_test
cargo test intel_4002_state_machine_test
cargo test intel_4003_state_machine_test
cargo test intel_4004_state_machine_test
# Mock-based tests only
cargo test mock_based_tests
# Integration tests
# Property-based tests only
cargo test property_based_tests
# Integration tests only
cargo test integration_tests
# JSON configuration tests
cargo test json_integration_tests
# Simple/core tests
cargo test simple_test
# Demo tests only
cargo test demo
```
### Run with Detailed Output
@ -113,13 +104,23 @@ cargo test test_name
## Test Architecture
### Test Infrastructure
### Mock System
The test suite uses the shared test library (`lib.rs`) which provides:
The test suite includes a comprehensive mock system that provides:
- **Helper functions**: Common test utilities for component creation and configuration
- **Shared assertions**: Reusable assertion patterns for state machine testing
- **Test fixtures**: Pre-configured component setups for common test scenarios
- **MockPin**: Simulates pin behavior with operation counting
- **MockIntel400xComponent**: Full component mock implementing all traits
- **MockScenario**: Test scenario builder with common setups
- **MockTimeProvider**: Deterministic time source for timing tests
### Property-Based Testing
Uses `proptest` to verify:
- State machine invariants hold for all inputs
- Type conversions are consistent
- Address assembly works for all valid inputs
- Timing constraints are maintained
### Integration Testing
@ -166,12 +167,12 @@ Tests verify that:
## Adding New Tests
When adding new functionality, add corresponding tests:
When adding new functionality to `intel_400x.rs`, add corresponding tests:
1. **Unit tests** for pure functions in `intel_400x_tests.rs`
2. **State machine tests** for component behavior in `intel_400x_state_machine_test.rs`
3. **Integration tests** for concrete usage in `integration_tests.rs`
4. **JSON config tests** for system configuration in `json_integration_tests.rs`
2. **Mock tests** for hardware interactions in `mock_based_tests.rs`
3. **Property tests** for behavioral properties in `property_based_tests.rs`
4. **Integration tests** for concrete usage in `integration_tests.rs`
## Test Data
@ -184,11 +185,12 @@ The tests use realistic data patterns that reflect actual Intel 4004/4001 usage:
## Dependencies
The test suite uses standard Rust testing:
The test suite uses these testing libraries:
- `proptest`: Property-based testing
- `mockall`: Mock generation (if needed)
- `pretty_assertions`: Enhanced assertion messages
- `std::time`: Timing simulation
- `serde_json`: JSON configuration parsing (for integration tests)
- Standard `#[test]` attributes with `cargo test`
## Continuous Integration

609
tests/fibonacci_test.rs
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@ -1,609 +0,0 @@
//! Fibonacci Program Verification Test
//!
//! This test verifies that the fibonacci.bin program executes correctly
//! on the Intel 4004 emulator by directly driving the CPU and ROM through
//! their state machines.
use rusty_emu::component::Component;
use rusty_emu::components::cpu::intel_4004::Intel4004;
use rusty_emu::components::memory::intel_4001::Intel4001;
use rusty_emu::connection::connect_pins;
use rusty_emu::pin::PinValue;
/// Read the fibonacci binary from file
fn get_fibonacci_program() -> Vec<u8> {
std::fs::read("programs/fibonacci.bin").expect("Failed to read fibonacci.bin")
}
/// Helper to create a connected CPU + ROM system for testing
struct TestSystem {
cpu: Intel4004,
rom: Intel4001,
}
impl TestSystem {
fn new(program: &[u8]) -> Self {
let cpu = Intel4004::new("CPU".to_string(), 750000.0);
let mut rom = Intel4001::new_with_access_time("ROM".to_string(), 1); // 1ns access time for fast tests
// Load program into ROM
rom.load_rom_data(program.to_vec(), 0).expect("Failed to load program");
TestSystem {
cpu,
rom,
}
}
fn connect(&mut self) {
// Connect data bus pins (D0-D3)
for i in 0..4 {
let pin_name = format!("D{}", i);
let cpu_pin = self.cpu.get_pin(&pin_name).unwrap();
let rom_pin = self.rom.get_pin(&pin_name).unwrap();
connect_pins(cpu_pin, rom_pin).unwrap();
}
// Connect SYNC
{
let cpu_pin = self.cpu.get_pin("SYNC").unwrap();
let rom_pin = self.rom.get_pin("SYNC").unwrap();
connect_pins(cpu_pin, rom_pin).unwrap();
}
// Connect CM
{
let cpu_pin = self.cpu.get_pin("CM").unwrap();
let rom_pin = self.rom.get_pin("CM").unwrap();
connect_pins(cpu_pin, rom_pin).unwrap();
}
// Connect clock pins
{
let cpu_phi1 = self.cpu.get_pin("PHI1").unwrap();
let rom_phi1 = self.rom.get_pin("PHI1").unwrap();
connect_pins(cpu_phi1, rom_phi1).unwrap();
}
{
let cpu_phi2 = self.cpu.get_pin("PHI2").unwrap();
let rom_phi2 = self.rom.get_pin("PHI2").unwrap();
connect_pins(cpu_phi2, rom_phi2).unwrap();
}
// Connect RESET
{
let cpu_pin = self.cpu.get_pin("RESET").unwrap();
let rom_pin = self.rom.get_pin("RESET").unwrap();
connect_pins(cpu_pin, rom_pin).unwrap();
}
}
/// Set clock pins - drive on CPU side only, they propagate to ROM via connected pins
fn set_clock(&self, phi1: PinValue, phi2: PinValue) {
if let Ok(pin) = self.cpu.get_pin("PHI1") {
pin.lock().set_driver(Some("clock".to_string()), phi1);
pin.lock().propagate();
}
if let Ok(pin) = self.cpu.get_pin("PHI2") {
pin.lock().set_driver(Some("clock".to_string()), phi2);
pin.lock().propagate();
}
}
/// Run a single clock half-cycle (just PHI1 or PHI2)
/// Update order depends on clock phase:
/// - PHI1↑ (address phase): CPU first (drives address), then ROM (latches address)
/// - PHI2↑ (data phase): ROM first (drives data), then CPU (reads data)
fn half_cycle(&mut self, phi1: PinValue, phi2: PinValue) {
self.set_clock(phi1, phi2);
if phi1 == PinValue::High {
// PHI1↑: CPU drives address, ROM latches it
self.cpu.update();
self.rom.update();
} else {
// PHI2↑: ROM drives data, CPU reads it
self.rom.update();
self.cpu.update();
}
}
/// Run a full clock cycle: PHI1 high → PHI2 high
fn clock_cycle(&mut self) {
self.half_cycle(PinValue::High, PinValue::Low);
self.half_cycle(PinValue::Low, PinValue::High);
}
/// Run multiple clock cycles
fn run_cycles(&mut self, n: u64) {
for _ in 0..n {
self.clock_cycle();
}
}
/// Get CPU program counter
fn get_pc(&self) -> u16 {
self.cpu.get_program_counter()
}
/// Get CPU accumulator
fn get_acc(&self) -> u8 {
self.cpu.get_accumulator()
}
/// Get CPU register
fn get_reg(&self, reg: u8) -> u8 {
self.cpu.get_register(reg).unwrap_or(0xFF)
}
/// Get CPU carry flag
fn get_carry(&self) -> bool {
self.cpu.get_carry()
}
}
/// Test that the fibonacci program can be loaded
#[test]
fn test_fibonacci_program_loads() {
let program = get_fibonacci_program();
println!("Fibonacci program: {} bytes", program.len());
assert_eq!(program[0], 0x20, "First byte should be FIM opcode (0x20)");
}
/// Test that cpu.update() doesn't hang
#[test]
fn test_cpu_update_single_step() {
let program = vec![0x00];
let mut sys = TestSystem::new(&program);
sys.connect();
sys.cpu.set_running(true);
sys.rom.set_running(true);
sys.cpu.update();
println!("PC={:03X} ACC={}", sys.get_pc(), sys.get_acc());
}
/// Test that rom.update() doesn't hang
#[test]
fn test_rom_update_single_step() {
let program = vec![0x00];
let mut sys = TestSystem::new(&program);
sys.connect();
sys.cpu.set_running(true);
sys.rom.set_running(true);
sys.rom.update();
}
/// Test that both update() calls work together
#[test]
fn test_both_update_single_step() {
let program = vec![0x00];
let mut sys = TestSystem::new(&program);
sys.connect();
sys.cpu.set_running(true);
sys.rom.set_running(true);
sys.cpu.update();
sys.rom.update();
println!("PC={:03X} ACC={}", sys.get_pc(), sys.get_acc());
}
/// Test FIM instruction (two-byte) loads register pair correctly
#[test]
fn test_fim_from_rom() {
// FIM R0/R1, 0x42 (opcode 0x20, data 0x42)
let program = vec![0x20, 0x42, 0x00];
let mut sys = TestSystem::new(&program);
sys.connect();
sys.cpu.set_running(true);
sys.rom.set_running(true);
// Run enough cycles for the two-byte FIM instruction
// FIM needs 2 instruction fetches (byte1 + byte2), each takes ~5 clock cycles
sys.run_cycles(15);
// FIM rpair 0 with data 0x42: R0 = 4, R1 = 2
assert_eq!(sys.get_reg(0), 4, "R0 should be 4 (high nibble of 0x42)");
assert_eq!(sys.get_reg(1), 2, "R1 should be 2 (low nibble of 0x42)");
assert_eq!(sys.get_pc(), 2, "PC should be at 0x002 after FIM");
}
/// Test a sequence of single-byte instructions: LDM + NOP + LDM
#[test]
fn test_single_byte_sequence() {
// LDM 5 (0xD5), NOP (0x00), LDM 3 (0xD3)
let program = vec![0xD5, 0x00, 0xD3];
let mut sys = TestSystem::new(&program);
sys.connect();
sys.cpu.set_running(true);
sys.rom.set_running(true);
// Run enough cycles for 3 single-byte instructions
sys.run_cycles(20);
// After LDM 5, NOP, LDM 3: ACC should be 3
assert_eq!(sys.get_acc(), 3, "ACC should be 3 after LDM 3");
assert_eq!(sys.get_pc(), 3, "PC should be at 0x003 after 3 instructions");
}
/// Test IAC (increment accumulator) instruction
#[test]
fn test_iac_instruction() {
// LDM 5 (0xD5), IAC (0xF2)
let program = vec![0xD5, 0xF2];
let mut sys = TestSystem::new(&program);
sys.connect();
sys.cpu.set_running(true);
sys.rom.set_running(true);
sys.run_cycles(15);
assert_eq!(sys.get_acc(), 6, "ACC should be 6 after LDM 5 + IAC");
}
/// Test ADD instruction
#[test]
fn test_add_instruction() {
// FIM R0/R1, 0x32 (R0=3, R1=2), LD R1 (0xA1), ADD R0 (0x80)
let program = vec![0x20, 0x32, 0xA1, 0x80];
let mut sys = TestSystem::new(&program);
sys.connect();
sys.cpu.set_running(true);
sys.rom.set_running(true);
sys.run_cycles(25);
// R0=3, R1=2, LD R1 → ACC=2, ADD R0 → ACC=2+3+carry(0)=5
assert_eq!(sys.get_acc(), 5, "ACC should be 5 after LD R1(2) + ADD R0(3)");
}
/// Test the actual fibonacci.bin program
///
/// The fibonacci.bin program computes Fibonacci numbers and stores them in RAM.
/// According to programs/README.md, it uses: LDM, LD, WRM, IAC, ADD, JCN, NOP
/// and stores results in RAM locations 0-7.
///
/// Since we don't have RAM connected, we verify that the program runs without
/// hanging by checking that the PC advances through the expected instruction
/// sequence.
#[test]
fn test_fibonacci_program_executes() {
let program = get_fibonacci_program();
println!("Fibonacci program: {} bytes", program.len());
for (i, b) in program.iter().enumerate() {
print!("{:02X} ", b);
if (i + 1) % 16 == 0 { println!(); }
}
println!();
let mut sys = TestSystem::new(&program);
sys.connect();
sys.cpu.set_running(true);
sys.rom.set_running(true);
// Run the program for enough cycles to execute several instructions
// The fibonacci program is 33 bytes, so ~16 instructions
// Each instruction takes ~5 clock cycles (A1+A2+A3+M1+M2 = 5 half-cycle pairs)
// Two-byte instructions take ~10 cycles
// Run for 200 cycles to cover the full program
sys.run_cycles(200);
let pc = sys.get_pc();
let acc = sys.get_acc();
println!("After 200 cycles: PC={:03X} ACC={}", pc, acc);
// The program should have advanced well past the initial instructions
// and should be executing somewhere in the program
assert!(pc > 0, "PC should have advanced from 0");
}
/// Test a simple fibonacci computation using direct instruction execution
/// This verifies the core computation without needing RAM:
/// F(0)=1, F(1)=1, F(2)=2, F(3)=3, F(4)=5
#[test]
fn test_fibonacci_computation_manual() {
// Manual fibonacci: compute F(n) using registers
// R0/R1 = F(prev), F(curr) via FIM
// Loop: LD R1, XCH R0, ADD R1 (F(prev)+F(curr))
// But let's just verify individual instructions work:
// FIM R0/R1, 0x11 → R0=1, R1=1 (fib initial values)
// LD R1 (0xA1) → ACC = R1 = 1
// XCH R0 (0xB0) → ACC = R0 = 1, R0 = 1 (was ACC)
// ADD R1 (0x81) → ACC = 1 + 1 = 2 (new fib number)
// XCH R1 (0xB1) → R1 = 2, ACC = 1 (old R1)
// XCH R0 (0xB0) → R0 = 1, ACC = 1 (old R0)
// Now R0=1, R1=2 (next fib pair)
let program = vec![
0x20, 0x11, // FIM R0/R1, 0x11 → R0=1, R1=1
0xA1, // LD R1 → ACC=1
0xB0, // XCH R0 → ACC=R0=1, R0=1
0x81, // ADD R1 → ACC=1+1+0=2
0xB1, // XCH R1 → R1=2, ACC=1
0xB0, // XCH R0 → R0=1, ACC=1
];
let mut sys = TestSystem::new(&program);
sys.connect();
sys.cpu.set_running(true);
sys.rom.set_running(true);
sys.run_cycles(40);
println!("R0={} R1={} ACC={} PC={:03X}",
sys.get_reg(0), sys.get_reg(1), sys.get_acc(), sys.get_pc());
// After the sequence: R0=1, R1=2
assert_eq!(sys.get_reg(0), 1, "R0 should be 1 (previous fib)");
assert_eq!(sys.get_reg(1), 2, "R1 should be 2 (current fib)");
}
/// Test ISZ (increment and skip if not zero) instruction
#[test]
fn test_isz_instruction() {
// FIM R2/R3, 0x09 → R2=0, R3=9
// ISZ R2, addr → R2 becomes 1 (not zero → jump back)
// But we need the jump target, so let's test the non-jump case:
// FIM R2/R3, 0xF9 → R2=0xF, R3=9
// ISZ R2, addr → R2 becomes 0 (wraps, zero → no jump, fall through)
let program = vec![
0x22, 0xF9, // FIM R2/R3, 0xF9 → R2=0xF, R3=9
0x72, 0x00, // ISZ R2, 0x00 → R2 becomes 0 (0xF+1=0x10&0xF=0), no jump
];
let mut sys = TestSystem::new(&program);
sys.connect();
sys.cpu.set_running(true);
sys.rom.set_running(true);
sys.run_cycles(30);
// R2 should be 0 (incremented from 0xF, wrapped to 0)
assert_eq!(sys.get_reg(2), 0, "R2 should be 0 after ISZ wraps");
// PC should be past the ISZ instruction (at least 4)
assert!(sys.get_pc() >= 4, "PC should be past ISZ (>= 4), got {}", sys.get_pc());
}
/// Test JCN (jump conditional) instruction
#[test]
fn test_jcn_instruction() {
// LDM 0 (0xD0) → ACC=0
// JCN 0x02, 0x00 → jump if ACC zero (bit 1 = ACC zero per datasheet)
let program = vec![
0xD0, // LDM 0 → ACC=0
0x12, 0x00, // JCN 0x2 (ACC zero), addr 0x00 → jump taken
];
let mut sys = TestSystem::new(&program);
sys.connect();
sys.cpu.set_running(true);
sys.rom.set_running(true);
sys.run_cycles(20);
// JCN should have jumped back to 0x00, creating a loop
// After 20 cycles, we should be somewhere in the loop
let pc = sys.get_pc();
println!("PC={:03X} ACC={}", pc, sys.get_acc());
assert!(pc <= 3, "PC should be in the loop (0-3), got {:03X}", pc);
}
/// Test JCN not taken
#[test]
fn test_jcn_not_taken() {
// LDM 5 (0xD5) → ACC=5 (not zero)
// JCN 0x02, 0x00 → jump if ACC zero → should NOT jump
let program = vec![
0xD5, // LDM 5 → ACC=5
0x12, 0x00, // JCN 0x2 (ACC zero), addr 0x00 → NOT taken
0xD0, // LDM 0 → ACC=0 (should reach here)
];
let mut sys = TestSystem::new(&program);
sys.connect();
sys.cpu.set_running(true);
sys.rom.set_running(true);
sys.run_cycles(25);
// Should have fallen through JCN, executed LDM 0, then continued
// Eventually hitting NOPs (0x00 bytes in uninitialized ROM)
assert_eq!(sys.get_acc(), 0, "ACC should be 0 after LDM 0");
}
/// Test INC instruction
#[test]
fn test_inc_instruction() {
// FIM R0/R1, 0x05 → R0=0, R1=5
// INC R1 (0x61) → R1 becomes 6
let program = vec![
0x20, 0x05, // FIM R0/R1, 0x05 → R0=0, R1=5
0x61, // INC R1 → R1=6
];
let mut sys = TestSystem::new(&program);
sys.connect();
sys.cpu.set_running(true);
sys.rom.set_running(true);
sys.run_cycles(20);
assert_eq!(sys.get_reg(1), 6, "R1 should be 6 after INC");
}
/// Full fibonacci sequence test using a simple loop
/// This program computes F(0)..F(7) and stores them in registers
#[test]
fn test_fibonacci_sequence_in_registers() {
// Compute fibonacci numbers in registers:
// R0 = F(n-1), R1 = F(n), R2 = counter
//
// FIM R0/R1, 0x11 → R0=1, R1=1
// FIM R2/R3, 0x70 → R2=7, R3=0 (loop counter = 7 iterations)
// Loop:
// LD R1 (0xA1) → ACC = F(n)
// XCH R0 (0xB0) → ACC = F(n-1), R0 = F(n)
// ADD R1 (0x81) → ACC = F(n-1) + F(n) = F(n+1)
// XCH R1 (0xB1) → R1 = F(n+1), ACC = F(n) (old)
// Wait, that's wrong. Let me reconsider.
//
// Actually: to compute F(n+1) = F(n) + F(n-1):
// LD R1 → ACC = F(n)
// ADD R0 → ACC = F(n) + F(n-1) = F(n+1) (with carry, need CLB first)
// XCH R0 → R0 = F(n+1), ACC = F(n) (old R0 was overwritten)
// Wait no, XCH swaps. Let me think more carefully.
//
// State: R0=F(n-1), R1=F(n)
// Goal: R0=F(n), R1=F(n+1)=F(n)+F(n-1)
//
// CLB (0xF0) → ACC=0, Carry=0
// LD R1 (0xA1) → ACC = F(n)
// ADD R0 (0x80) → ACC = F(n) + F(n-1) + 0 = F(n+1)
// XCH R1 (0xB1) → R1 = F(n+1), ACC = F(n) (old F(n))
// XCH R0 (0xB0) → R0 = F(n), ACC = F(n-1) (old F(n-1), but we don't care)
// ISZ R2, loop → R2++, jump if not zero
//
// Expected sequence: R0=1, R1=1 → R0=1, R1=2 → R0=2, R1=3 → R0=3, R1=5 →
// R0=5, R1=8 → R0=8, R1=13 → R0=13, R1=21 → R0=21, R1=34
// But 4-bit registers max at 15! So this only works for small values.
// Let's do just 3 iterations to stay in 4-bit range:
// R0=1, R1=1 → R0=1, R1=2 → R0=2, R1=3 → R0=3, R1=5
// Program:
// 0x00: 0x20 0x11 FIM R0/R1, 0x11 → R0=1, R1=1
// 0x02: 0x22 0x30 FIM R2/R3, 0x30 → R2=3, R3=0
// 0x04: 0xF0 CLB (ACC=0, Carry=0)
// 0x05: 0xA1 LD R1
// 0x06: 0x80 ADD R0
// 0x07: 0xB1 XCH R1
// 0x08: 0xB0 XCH R0
// 0x09: 0x72 0x04 ISZ R2, 0x04 (jump to 0x04 if R2 not zero after inc)
let program = vec![
0x20, 0x11, // addr 0: FIM R0/R1, 0x11
0x22, 0x30, // addr 2: FIM R2/R3, 0x30
0xF0, // addr 4: CLB
0xA1, // addr 5: LD R1
0x80, // addr 6: ADD R0
0xB1, // addr 7: XCH R1
0xB0, // addr 8: XCH R0
0x72, 0x04, // addr 9: ISZ R2, 0x04
];
let mut sys = TestSystem::new(&program);
sys.connect();
sys.cpu.set_running(true);
sys.rom.set_running(true);
// Run enough cycles for the loop
// 2 two-byte FIM + 3 iterations of (CLB + LD + ADD + XCH + XCH + ISZ)
// = 2*2 + 3*(5+2) = 4 + 21 = 25 instruction bytes
// Each single-byte instruction takes ~5 cycles, two-byte ~10 cycles
sys.run_cycles(150);
let r0 = sys.get_reg(0);
let r1 = sys.get_reg(1);
let r2 = sys.get_reg(2);
let pc = sys.get_pc();
println!("R0={} R1={} R2={} PC={:03X} ACC={}",
r0, r1, r2, pc, sys.get_acc());
// After 3 iterations:
// Iter 1: R0=1, R1=1+1=2 → R0=1, R1=2
// Iter 2: R0=2, R1=1+2=3 → wait, let me re-trace
//
// Initial: R0=1, R1=1, R2=3
// Iter 1: CLB, LD R1→ACC=1, ADD R0→ACC=1+1=2, XCH R1→R1=2,ACC=1, XCH R0→R0=1,ACC=1
// Wait, XCH R1 swaps ACC(2) with R1(1) → R1=2, ACC=1
// XCH R0 swaps ACC(1) with R0(1) → R0=1, ACC=1
// ISZ R2: R2=3→4, not zero → jump
// State: R0=1, R1=2, R2=4
// Iter 2: CLB, LD R1→ACC=2, ADD R0→ACC=2+1=3, XCH R1→R1=3,ACC=2, XCH R0→R0=2,ACC=1
// ISZ R2: R2=4→5, not zero → jump
// State: R0=2, R1=3, R2=5
// Iter 3: CLB, LD R1→ACC=3, ADD R0→ACC=3+2=5, XCH R1→R1=5,ACC=3, XCH R0→R0=3,ACC=2
// ISZ R2: R2=5→6, not zero → jump
// State: R0=3, R1=5, R2=6
// Wait, R2 starts at 3 and increments. It wraps at 16 (4-bit).
// After 3 increments: 3→4→5→6, still not zero, so loop continues!
// We need R2 to start at a value that reaches 0 after 3 increments.
// 0xD (13) → 14 → 15 → 0 (zero after 3 increments)
// Actually, let me reconsider. ISZ increments and jumps if NOT zero.
// So with R2=3: inc→4 (not zero, jump), inc→5 (not zero, jump), inc→6 (not zero, jump)...
// It will loop 13 times until R2 wraps from 15 to 0!
// That's 13 iterations, which will overflow 4-bit registers.
// Let me use R2=0xD (13): inc→14 (jump), inc→15 (jump), inc→0 (no jump, fall through)
// That gives exactly 3 iterations.
// Let me redo with correct program:
// Actually, the test above uses R2=3 which will loop 13 times.
// The 4-bit registers will wrap. Let's see what happens:
// After enough iterations, R0 and R1 will contain fibonacci values mod 16.
// Let me just verify the first few iterations are correct by running fewer cycles.
// For now, let me just check that the program runs and produces some result.
// The key verification is that instruction fetch and execution work.
// With R2=3, after 13 iterations the ISZ falls through.
// Fibonacci mod 16: 1,1,2,3,5,8,13,5,2,7,9,0,9,9,2,11...
// After 13 iterations from R0=1,R1=1:
// F(0)=1, F(1)=1, F(2)=2, F(3)=3, F(4)=5, F(5)=8, F(6)=13, F(7)=5 (21 mod 16),
// F(8)=2 (34 mod 16), F(9)=7, F(10)=9, F(11)=0, F(12)=9, F(13)=9
// Hmm, this is getting complex. Let me just verify the program executes.
assert!(pc > 0, "PC should have advanced");
}
/// Simpler fibonacci test with correct counter
#[test]
fn test_fibonacci_three_iterations() {
// Same as above but R2 starts at 0xD (13) so it wraps to 0 after exactly 3 iterations
let program = vec![
0x20, 0x11, // addr 0: FIM R0/R1, 0x11 → R0=1, R1=1
0x22, 0xD0, // addr 2: FIM R2/R3, 0xD0 → R2=0xD (13), R3=0
0xF0, // addr 4: CLB
0xA1, // addr 5: LD R1
0x80, // addr 6: ADD R0
0xB1, // addr 7: XCH R1
0xB0, // addr 8: XCH R0
0x72, 0x04, // addr 9: ISZ R2, 0x04
];
let mut sys = TestSystem::new(&program);
sys.connect();
sys.cpu.set_running(true);
sys.rom.set_running(true);
sys.run_cycles(150);
let r0 = sys.get_reg(0);
let r1 = sys.get_reg(1);
let r2 = sys.get_reg(2);
let pc = sys.get_pc();
println!("R0={} R1={} R2={} PC={:03X} ACC={}",
r0, r1, r2, pc, sys.get_acc());
// After 3 iterations (R2: 13→14→15→0):
// Iter 1: R0=1, R1=2 (1+1)
// Iter 2: R0=2, R1=3 (2+1)
// Iter 3: R0=3, R1=5 (3+2)
// ISZ falls through, PC at 11
assert_eq!(r0, 3, "R0 should be 3 (F(n-1))");
assert_eq!(r1, 5, "R1 should be 5 (F(n))");
assert_eq!(r2, 0, "R2 should be 0 (counter wrapped)");
assert_eq!(pc, 11, "PC should be at 11 (past ISZ)");
}

45
tests/gui_integration_tests.rs
View file

@ -6,10 +6,9 @@
#![cfg(test)]
use parking_lot::Mutex;
use rusty_emu::gui::GuiApp;
use rusty_emu::system_config::{ConfigurableSystem, SystemFactory};
use std::sync::Arc;
use std::sync::{Arc, Mutex};
use std::thread;
use std::time::Duration;
@ -37,8 +36,7 @@ mod gui_integration_test_utils {
/// Note: This function acquires the lock internally. Do NOT call it while holding the lock.
pub fn simulate_gui_updates(system: &Arc<Mutex<ConfigurableSystem>>) {
// Simulate the kind of updates that would happen in the GUI thread
let system_guard = system.lock();
{
if let Ok(system_guard) = system.lock() {
// Simulate some system activity
let _ = system_guard.is_running(); // Access system state
}
@ -50,19 +48,14 @@ mod gui_integration_test_utils {
// Spawn a thread that accesses the system
let handle = thread::spawn(move || {
// Try to acquire the lock - return true if successful (parking_lot::lock always succeeds)
let _guard = system_clone.lock();
true
// Try to acquire the lock - return true if successful (regardless of is_running value)
system_clone.lock().is_ok()
});
// Main thread also accesses the system - but release lock before joining to avoid deadlock
{
let _guard = system.lock();
// Access the system while holding the lock
}
let main_thread_result = true;
// Main thread also accesses the system
let main_thread_result = system.lock().is_ok();
// Wait for spawned thread (lock is released, so no deadlock)
// Wait for spawned thread
let spawned_thread_result = handle.join().unwrap_or(false);
// Both threads should be able to acquire the lock without deadlock
@ -157,8 +150,7 @@ mod gui_system_integration_tests {
thread::spawn(move || {
// Simulate GUI update pattern
for _ in 0..10 {
let _system_guard = system_clone.lock();
{
if let Ok(_system_guard) = system_clone.lock() {
// Simulate some processing time
thread::sleep(Duration::from_micros(10));
}
@ -204,7 +196,7 @@ mod gui_system_integration_tests {
// Test the polling mechanism that GUI would use
for i in 0..10 {
{
let system_guard = system.lock();
let system_guard = system.lock().unwrap();
let is_running = system_guard.is_running();
// Simulate state updates that would happen in GUI
@ -229,7 +221,7 @@ mod gui_system_integration_tests {
// In a real implementation, this would test actual memory access
{
let system_guard = system.lock();
let system_guard = system.lock().unwrap();
// Test that system provides memory information
let _ = system_guard.get_system_info(); // Access system info
} // system_guard is dropped here
@ -249,7 +241,7 @@ mod gui_system_integration_tests {
// Test register state structure for GUI integration
{
let _system_guard = system.lock();
let _system_guard = system.lock().unwrap();
// In a real implementation, this would access actual CPU registers
// For now, we test the GUI state structure
}
@ -270,7 +262,7 @@ mod gui_system_integration_tests {
// Test component state monitoring for GUI
{
let system_guard = system.lock();
let system_guard = system.lock().unwrap();
let components = system_guard.get_components();
// Test that components are accessible (GUI would monitor these)
@ -442,19 +434,18 @@ mod gui_error_handling_tests {
// Hold the lock for a short time to simulate contention
let system_clone = Arc::clone(&system);
let lock_handle = thread::spawn(move || {
let _system_guard = system_clone.lock();
{
if let Ok(_system_guard) = system_clone.lock() {
thread::sleep(Duration::from_millis(10));
}
});
// Try to access from main thread (should not deadlock)
let access_result = system.try_lock().is_some();
let access_result = system.try_lock().is_ok();
lock_handle.join().unwrap();
// Should be able to access after the lock is released
assert!(access_result || system.try_lock().is_some());
assert!(access_result || system.try_lock().is_ok());
}
#[test]
@ -490,7 +481,7 @@ mod gui_real_time_tests {
for i in 0..20 {
{
let _system_guard = system.lock();
let _system_guard = system.lock().unwrap();
// Simulate GUI state polling
update_count += 1;
@ -544,7 +535,7 @@ mod gui_real_time_tests {
// For now, we test the data structures are compatible
{
let _system_guard = system.lock();
let _system_guard = system.lock().unwrap();
// Test memory data structure compatibility
}
@ -568,7 +559,7 @@ mod gui_real_time_tests {
let system = create_test_system();
{
let _system_guard = system.lock();
let _system_guard = system.lock().unwrap();
}
let mut gui_state = rusty_emu::gui::state::GuiState::new();

6
tests/gui_tests.rs
View file

@ -6,10 +6,9 @@
#![cfg(test)]
use eframe::egui;
use parking_lot::Mutex;
use rusty_emu::gui::components::*;
use rusty_emu::gui::state::*;
use std::sync::Arc;
use std::sync::{Arc, Mutex};
/// Test utilities for GUI testing
mod gui_test_utils {
@ -305,8 +304,7 @@ mod gui_integration_tests {
// For now, we verify the components exist and have valid state
// Test control panel rendering (would panic if component is invalid)
// Note: render_control_panel now takes an optional system parameter
components.render_control_panel(&mut create_test_ui(&ctx), &mut state, None);
components.render_control_panel(&mut create_test_ui(&ctx), &mut state);
// Test memory viewer rendering
components.render_memory_viewer(&mut create_test_ui(&ctx), &mut state);

4
tests/integration_tests.rs
View file

@ -81,8 +81,8 @@ mod intel_4001_integration_tests {
// Test access time configuration
assert_eq!(rom.get_access_time(), 1);
// Test address latch time handling (virtual time: Duration-based)
let test_time = std::time::Duration::from_nanos(500);
// Test address latch time handling
let test_time = std::time::Instant::now();
rom.set_address_latch_time(Some(test_time));
assert_eq!(rom.get_address_latch_time(), Some(test_time));
}

220
tests/intel_4001_state_machine_test.rs
View file

@ -38,8 +38,8 @@ fn test_intel_4001_state_machine_progression() {
// Initialize clock pins to Low
{
let mut phi1_guard = phi1_pin.lock();
let mut phi2_guard = phi2_pin.lock();
let mut phi1_guard = phi1_pin.lock().unwrap();
let mut phi2_guard = phi2_pin.lock().unwrap();
phi1_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
phi2_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
}
@ -47,10 +47,10 @@ fn test_intel_4001_state_machine_progression() {
// Initialize control pins
// Note: RESET is active LOW, so set it to High to ensure component is not in reset
{
let mut sync_guard = sync_pin.lock();
let mut cm_guard = cm_pin.lock();
let mut ci_guard = ci_pin.lock();
let mut reset_guard = reset_pin.lock();
let mut sync_guard = sync_pin.lock().unwrap();
let mut cm_guard = cm_pin.lock().unwrap();
let mut ci_guard = ci_pin.lock().unwrap();
let mut reset_guard = reset_pin.lock().unwrap();
sync_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
cm_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
ci_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
@ -59,10 +59,10 @@ fn test_intel_4001_state_machine_progression() {
// Initialize data pins to Low
{
let mut d0_guard = d0_pin.lock();
let mut d1_guard = d1_pin.lock();
let mut d2_guard = d2_pin.lock();
let mut d3_guard = d3_pin.lock();
let mut d0_guard = d0_pin.lock().unwrap();
let mut d1_guard = d1_pin.lock().unwrap();
let mut d2_guard = d2_pin.lock().unwrap();
let mut d3_guard = d3_pin.lock().unwrap();
d0_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
d1_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
d2_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
@ -78,9 +78,9 @@ fn test_intel_4001_state_machine_progression() {
// Set up memory read operation: SYNC=1, CM=1, CI=0 (memory access)
{
let mut sync_guard = sync_pin.lock();
let mut cm_guard = cm_pin.lock();
let mut ci_guard = ci_pin.lock();
let mut sync_guard = sync_pin.lock().unwrap();
let mut cm_guard = cm_pin.lock().unwrap();
let mut ci_guard = ci_pin.lock().unwrap();
sync_guard.set_driver(Some("TEST".to_string()), PinValue::High);
cm_guard.set_driver(Some("TEST".to_string()), PinValue::High);
ci_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Memory access
@ -88,10 +88,10 @@ fn test_intel_4001_state_machine_progression() {
// Set up address high nibble (0x1 for address 0x12)
{
let mut d0_guard = d0_pin.lock();
let mut d1_guard = d1_pin.lock();
let mut d2_guard = d2_pin.lock();
let mut d3_guard = d3_pin.lock();
let mut d0_guard = d0_pin.lock().unwrap();
let mut d1_guard = d1_pin.lock().unwrap();
let mut d2_guard = d2_pin.lock().unwrap();
let mut d3_guard = d3_pin.lock().unwrap();
// 0x1 = 0001 (D0=1, D1=0, D2=0, D3=0)
d0_guard.set_driver(Some("TEST".to_string()), PinValue::High);
d1_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
@ -104,7 +104,7 @@ fn test_intel_4001_state_machine_progression() {
// Trigger Φ1 rising edge to start memory operation and latch high nibble
{
let mut phi1_guard = phi1_pin.lock();
let mut phi1_guard = phi1_pin.lock().unwrap();
phi1_guard.set_driver(Some("TEST".to_string()), PinValue::High);
}
@ -120,7 +120,7 @@ fn test_intel_4001_state_machine_progression() {
// Reset Φ1 to Low
{
let mut phi1_guard = phi1_pin.lock();
let mut phi1_guard = phi1_pin.lock().unwrap();
phi1_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
}
@ -129,10 +129,10 @@ fn test_intel_4001_state_machine_progression() {
// Set up address low nibble (0x2 for address 0x12)
{
let mut d0_guard = d0_pin.lock();
let mut d1_guard = d1_pin.lock();
let mut d2_guard = d2_pin.lock();
let mut d3_guard = d3_pin.lock();
let mut d0_guard = d0_pin.lock().unwrap();
let mut d1_guard = d1_pin.lock().unwrap();
let mut d2_guard = d2_pin.lock().unwrap();
let mut d3_guard = d3_pin.lock().unwrap();
// 0x2 = 0010 (D0=0, D1=1, D2=0, D3=0)
d0_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
d1_guard.set_driver(Some("TEST".to_string()), PinValue::High);
@ -143,117 +143,107 @@ fn test_intel_4001_state_machine_progression() {
// Wait for pins to settle
thread::sleep(Duration::from_millis(1));
// Trigger Φ1 rising edge again - ROM latches low nibble on PHI1 rising edge
// (address nibbles are latched on Φ1 RISING edge, same as CPU drives address)
// Trigger Φ1 rising edge again - ROM should stay in AddressPhase
// (address nibbles are latched on Φ1 falling edge, not rising)
{
let mut phi1_guard = phi1_pin.lock();
let mut phi1_guard = phi1_pin.lock().unwrap();
phi1_guard.set_driver(Some("TEST".to_string()), PinValue::High);
}
// Update to process Φ1 rising edge
rom.update();
// Should have latched low nibble and transitioned to WaitLatency
// (both nibbles latched on successive PHI1 rising edges)
// Should still be in AddressPhase (latching happens on falling edge)
assert_eq!(
rom.get_timing_state(),
TimingState::AddressPhase,
"Should still be in AddressPhase after Φ1 rising - latching happens on falling edge"
);
println!(
"State after Φ1 rising (before falling): {:?}",
rom.get_timing_state()
);
// Reset Φ1 to Low to trigger falling edge - this is when low nibble is latched
{
let mut phi1_guard = phi1_pin.lock().unwrap();
phi1_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
}
// Update to process Φ1 falling edge - low nibble is latched here
rom.update();
// Should have latched low nibble and transitioned to WaitLatency or DriveData
// With 1ns access time, it might transition directly to DriveData
let state_after_low_nibble = rom.get_timing_state();
assert!(
state_after_low_nibble == TimingState::WaitLatency,
"Expected WaitLatency after latching both nibbles on PHI1 rising, got {:?}",
state_after_low_nibble == TimingState::WaitLatency
|| state_after_low_nibble == TimingState::DriveData,
"Expected WaitLatency or DriveData after latching both nibbles, got {:?}",
state_after_low_nibble
);
println!(
"State after second Φ1 rising (both nibbles latched): {:?}",
"State after Φ1 falling (low nibble latched): {:?}",
state_after_low_nibble
);
// Remove test drivers from data pins to allow ROM to drive bus
{
let mut d0_guard = d0_pin.lock();
let mut d1_guard = d1_pin.lock();
let mut d2_guard = d2_pin.lock();
let mut d3_guard = d3_pin.lock();
let mut d0_guard = d0_pin.lock().unwrap();
let mut d1_guard = d1_pin.lock().unwrap();
let mut d2_guard = d2_pin.lock().unwrap();
let mut d3_guard = d3_pin.lock().unwrap();
d0_guard.remove_driver("TEST");
d1_guard.remove_driver("TEST");
d2_guard.remove_driver("TEST");
d3_guard.remove_driver("TEST");
}
// ROM is in WaitLatency with a3_wait_cycles=1.
// Need to cycle the clock to get through the wait period and into DriveData.
// The ROM expects PHI2 rising edges to decrement a3_wait_cycles and transition.
// Step 1: PHI1 falling + PHI2 rising (decrements a3_wait_cycles to 0)
{
let mut phi1_guard = phi1_pin.lock();
phi1_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
}
{
let mut phi2_guard = phi2_pin.lock();
phi2_guard.set_driver(Some("TEST".to_string()), PinValue::High);
}
rom.update();
// a3_wait_cycles decremented from 1 to 0
// If still in WaitLatency, trigger Φ2 rising edge to check latency and drive data
if rom.get_timing_state() == TimingState::WaitLatency {
// Trigger Φ2 rising edge
{
let mut phi2_guard = phi2_pin.lock().unwrap();
phi2_guard.set_driver(Some("TEST".to_string()), PinValue::High);
}
// Step 2: PHI2 falling + PHI1 rising (no transition yet, just clock edge)
{
let mut phi2_guard = phi2_pin.lock();
phi2_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
}
{
let mut phi1_guard = phi1_pin.lock();
phi1_guard.set_driver(Some("TEST".to_string()), PinValue::High);
}
rom.update();
// Update to process Φ2 rising edge
rom.update();
// Step 3: PHI1 falling + PHI2 rising (a3_wait_cycles=0, transitions to DriveData)
{
let mut phi1_guard = phi1_pin.lock();
phi1_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
// Should have transitioned to DriveData
assert_eq!(rom.get_timing_state(), TimingState::DriveData);
println!("State after Φ2 rising: {:?}", rom.get_timing_state());
}
{
let mut phi2_guard = phi2_pin.lock();
phi2_guard.set_driver(Some("TEST".to_string()), PinValue::High);
}
rom.update();
// Should now be in DriveData (process_latency_elapsed on this PHI2 rising)
// But return statement means data isn't driven yet
// Step 4: PHI2 falling + PHI1 rising
{
let mut phi2_guard = phi2_pin.lock();
phi2_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
}
{
let mut phi1_guard = phi1_pin.lock();
phi1_guard.set_driver(Some("TEST".to_string()), PinValue::High);
}
rom.update();
// Step 5: PHI1 falling + PHI2 rising - NOW ROM drives data
{
let mut phi1_guard = phi1_pin.lock();
phi1_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
}
{
let mut phi2_guard = phi2_pin.lock();
phi2_guard.set_driver(Some("TEST".to_string()), PinValue::High);
}
rom.update();
// Should be in DriveData and driving OPR (high nibble of 0xAB = 0xA)
assert_eq!(rom.get_timing_state(), TimingState::DriveData);
println!("State after PHI2 rising (driving data): {:?}", rom.get_timing_state());
// Wait for pins to settle after ROM drives data
thread::sleep(Duration::from_millis(1));
// Verify OPR is being driven on the bus
// Data 0xAB has high nibble 0xA = 1010 (D0=0, D1=1, D2=0, D3=1)
assert_eq!(d0_pin.lock().read(), PinValue::Low, "D0 should be Low for 0xA");
assert_eq!(d1_pin.lock().read(), PinValue::High, "D1 should be High for 0xA");
assert_eq!(d2_pin.lock().read(), PinValue::Low, "D2 should be Low for 0xA");
assert_eq!(d3_pin.lock().read(), PinValue::High, "D3 should be High for 0xA");
println!("OPR data verified: 0xA");
// Verify data is being driven on the bus
// Data 0xAB has low nibble 0xB = 1011 (D0=1, D1=1, D2=0, D3=1)
// Note: Due to bit ordering, D0 should be High, D1 should be High, D2 should be Low, D3 should be High
assert_eq!(d0_pin.lock().unwrap().read(), PinValue::High);
assert_eq!(d1_pin.lock().unwrap().read(), PinValue::High);
assert_eq!(d2_pin.lock().unwrap().read(), PinValue::Low);
assert_eq!(d3_pin.lock().unwrap().read(), PinValue::High);
// Reset Φ2 to Low
{
let mut phi2_guard = phi2_pin.lock().unwrap();
phi2_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
}
// Update to process Φ2 falling edge
rom.update();
// Should have returned to Idle
assert_eq!(rom.get_timing_state(), TimingState::Idle);
println!("Final state: {:?}", rom.get_timing_state());
// Verify data bus is tri-stated
assert_eq!(d0_pin.lock().unwrap().read(), PinValue::HighZ);
assert_eq!(d1_pin.lock().unwrap().read(), PinValue::HighZ);
assert_eq!(d2_pin.lock().unwrap().read(), PinValue::HighZ);
assert_eq!(d3_pin.lock().unwrap().read(), PinValue::HighZ);
}
/// Test to verify that unified state machine doesn't progress without proper control signals
@ -271,8 +261,8 @@ fn test_intel_4001_state_machine_no_progression_without_signals() {
// Initialize clock pins to Low
{
let mut phi1_guard = phi1_pin.lock();
let mut phi2_guard = phi2_pin.lock();
let mut phi1_guard = phi1_pin.lock().unwrap();
let mut phi2_guard = phi2_pin.lock().unwrap();
phi1_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
phi2_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
}
@ -285,7 +275,7 @@ fn test_intel_4001_state_machine_no_progression_without_signals() {
// Trigger clock edges without setting up control signals
{
let mut phi1_guard = phi1_pin.lock();
let mut phi1_guard = phi1_pin.lock().unwrap();
phi1_guard.set_driver(Some("TEST".to_string()), PinValue::High);
}
@ -297,7 +287,7 @@ fn test_intel_4001_state_machine_no_progression_without_signals() {
// Reset Φ1 to Low
{
let mut phi1_guard = phi1_pin.lock();
let mut phi1_guard = phi1_pin.lock().unwrap();
phi1_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
}
@ -306,7 +296,7 @@ fn test_intel_4001_state_machine_no_progression_without_signals() {
// Trigger Φ2 rising edge
{
let mut phi2_guard = phi2_pin.lock();
let mut phi2_guard = phi2_pin.lock().unwrap();
phi2_guard.set_driver(Some("TEST".to_string()), PinValue::High);
}
@ -335,7 +325,7 @@ fn test_intel_4001_state_machine_reset() {
// Initialize clock pins to Low
{
let mut phi1_guard = phi1_pin.lock();
let mut phi1_guard = phi1_pin.lock().unwrap();
phi1_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
}
@ -347,9 +337,9 @@ fn test_intel_4001_state_machine_reset() {
// Set up memory read operation: SYNC=1, CM=1, CI=0 (memory access)
{
let mut sync_guard = sync_pin.lock();
let mut cm_guard = cm_pin.lock();
let mut ci_guard = ci_pin.lock();
let mut sync_guard = sync_pin.lock().unwrap();
let mut cm_guard = cm_pin.lock().unwrap();
let mut ci_guard = ci_pin.lock().unwrap();
sync_guard.set_driver(Some("TEST".to_string()), PinValue::High);
cm_guard.set_driver(Some("TEST".to_string()), PinValue::High);
ci_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Memory access
@ -357,7 +347,7 @@ fn test_intel_4001_state_machine_reset() {
// Trigger Φ1 rising edge to start memory operation
{
let mut phi1_guard = phi1_pin.lock();
let mut phi1_guard = phi1_pin.lock().unwrap();
phi1_guard.set_driver(Some("TEST".to_string()), PinValue::High);
}
@ -369,7 +359,7 @@ fn test_intel_4001_state_machine_reset() {
// Assert RESET (active LOW - set to Low to trigger reset)
{
let mut reset_guard = reset_pin.lock();
let mut reset_guard = reset_pin.lock().unwrap();
reset_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
}

22
tests/intel_4002_state_machine_test.rs
View file

@ -32,8 +32,8 @@ fn create_test_ram() -> Intel4002 {
let phi1_pin = ram.get_pin("PHI1").unwrap();
let phi2_pin = ram.get_pin("PHI2").unwrap();
{
let mut phi1_guard = phi1_pin.lock();
let mut phi2_guard = phi2_pin.lock();
let mut phi1_guard = phi1_pin.lock().unwrap();
let mut phi2_guard = phi2_pin.lock().unwrap();
phi1_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
phi2_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
}
@ -55,7 +55,7 @@ fn set_data_bus(ram: &Intel4002, value: u8) {
for i in 0..4 {
if let Ok(pin) = ram.get_pin(&format!("D{}", i)) {
if let Some(mut pin_guard) = pin.try_lock() {
if let Ok(mut pin_guard) = pin.lock() {
let bit_value = (nibble >> i) & 1;
let pin_value = if bit_value == 1 {
PinValue::High
@ -74,7 +74,7 @@ fn set_data_bus(ram: &Intel4002, value: u8) {
fn clear_data_bus_drivers(ram: &Intel4002) {
for i in 0..4 {
if let Ok(pin) = ram.get_pin(&format!("D{}", i)) {
if let Some(mut pin_guard) = pin.try_lock() {
if let Ok(mut pin_guard) = pin.lock() {
pin_guard.remove_driver("TEST");
}
}
@ -90,8 +90,8 @@ fn generate_clock_edge(ram: &mut Intel4002, phi1_high: bool, phi2_high: bool) {
// Set clock pins
{
let mut phi1_guard = phi1_pin.lock();
let mut phi2_guard = phi2_pin.lock();
let mut phi1_guard = phi1_pin.lock().unwrap();
let mut phi2_guard = phi2_pin.lock().unwrap();
phi1_guard.set_driver(
Some("TEST".to_string()),
@ -217,16 +217,16 @@ fn test_ram_read_state_progression() {
// Read data bus value
let mut data_value = 0;
if d0_pin.lock().read() == PinValue::High {
if d0_pin.lock().unwrap().read() == PinValue::High {
data_value |= 1 << 0;
}
if d1_pin.lock().read() == PinValue::High {
if d1_pin.lock().unwrap().read() == PinValue::High {
data_value |= 1 << 1;
}
if d2_pin.lock().read() == PinValue::High {
if d2_pin.lock().unwrap().read() == PinValue::High {
data_value |= 1 << 2;
}
if d3_pin.lock().read() == PinValue::High {
if d3_pin.lock().unwrap().read() == PinValue::High {
data_value |= 1 << 3;
}
@ -470,7 +470,7 @@ fn test_reset_functionality() {
// Assert RESET (active low)
let reset_pin = ram.get_pin("RESET").unwrap();
{
let mut reset_guard = reset_pin.lock();
let mut reset_guard = reset_pin.lock().unwrap();
reset_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
}
wait_for_pin_settlement();

4
tests/intel_4003_state_machine_test.rs
View file

@ -13,7 +13,7 @@ use rusty_emu::pin::PinValue;
/// Test helper to set pin value with proper driver management
fn set_pin_value(component: &Intel4003, pin_name: &str, value: PinValue, driver: &str) {
if let Ok(pin) = component.get_pin(pin_name) {
if let Some(mut pin_guard) = pin.try_lock() {
if let Ok(mut pin_guard) = pin.lock() {
pin_guard.set_driver(Some(driver.to_string()), value);
}
}
@ -22,7 +22,7 @@ fn set_pin_value(component: &Intel4003, pin_name: &str, value: PinValue, driver:
/// Test helper to remove pin driver
fn remove_pin_driver(component: &Intel4003, pin_name: &str) {
if let Ok(pin) = component.get_pin(pin_name) {
if let Some(mut pin_guard) = pin.try_lock() {
if let Ok(mut pin_guard) = pin.lock() {
pin_guard.set_driver(None, PinValue::HighZ);
}
}

67
tests/intel_4004_state_machine_test.rs
View file

@ -3,8 +3,7 @@
//! This test verifies that the Intel 4004 CPU state machine progresses correctly
//! through all phases: Idle → AddressPhase → WaitLatency → DriveData → Idle
use parking_lot::Mutex;
use std::sync::Arc;
use std::sync::{Arc, Mutex};
use std::thread;
use std::time::{Duration, Instant};
@ -47,8 +46,16 @@ impl CpuTestHelper {
let phi2 = Arc::new(Mutex::new(Pin::new("PHI2".to_string())));
// Connect CPU to test clock
cpu.get_pin("PHI1").unwrap().lock().connect_to(phi1.clone());
cpu.get_pin("PHI2").unwrap().lock().connect_to(phi2.clone());
cpu.get_pin("PHI1")
.unwrap()
.lock()
.unwrap()
.connect_to(phi1.clone());
cpu.get_pin("PHI2")
.unwrap()
.lock()
.unwrap()
.connect_to(phi2.clone());
CpuTestHelper {
cpu,
@ -83,9 +90,11 @@ impl CpuTestHelper {
// Phase 1: Φ1 high, Φ2 low
self.phi1
.lock()
.unwrap()
.set_driver(Some("clock".to_string()), PinValue::High);
self.phi2
.lock()
.unwrap()
.set_driver(Some("clock".to_string()), PinValue::Low);
thread::sleep(Duration::from_millis(1));
@ -95,9 +104,11 @@ impl CpuTestHelper {
// Phase 2: Φ1 low, Φ2 high
self.phi1
.lock()
.unwrap()
.set_driver(Some("clock".to_string()), PinValue::Low);
self.phi2
.lock()
.unwrap()
.set_driver(Some("clock".to_string()), PinValue::High);
thread::sleep(Duration::from_millis(1));
@ -106,9 +117,11 @@ impl CpuTestHelper {
// Phase 3: Both low
self.phi1
.lock()
.unwrap()
.set_driver(Some("clock".to_string()), PinValue::Low);
self.phi2
.lock()
.unwrap()
.set_driver(Some("clock".to_string()), PinValue::Low);
thread::sleep(Duration::from_millis(1));
@ -124,18 +137,28 @@ impl CpuTestHelper {
}
fn set_control_pins(&self, sync: bool, cm: bool, reset: bool) {
self.cpu.get_pin("SYNC").unwrap().lock().set_driver(
Some("test".to_string()),
if sync { PinValue::High } else { PinValue::Low },
);
self.cpu.get_pin("CM").unwrap().lock().set_driver(
self.cpu
.get_pin("SYNC")
.unwrap()
.lock()
.unwrap()
.set_driver(
Some("test".to_string()),
if sync { PinValue::High } else { PinValue::Low },
);
self.cpu.get_pin("CM").unwrap().lock().unwrap().set_driver(
Some("test".to_string()),
if cm { PinValue::High } else { PinValue::Low },
);
self.cpu.get_pin("RESET").unwrap().lock().set_driver(
Some("test".to_string()),
if reset { PinValue::High } else { PinValue::Low },
);
self.cpu
.get_pin("RESET")
.unwrap()
.lock()
.unwrap()
.set_driver(
Some("test".to_string()),
if reset { PinValue::High } else { PinValue::Low },
);
}
fn drive_data_bus(&self, data: u8) {
@ -145,6 +168,7 @@ impl CpuTestHelper {
.get_pin(&format!("D{}", i))
.unwrap()
.lock()
.unwrap()
.set_driver(
Some("test".to_string()),
if bit_value == 1 {
@ -160,9 +184,10 @@ impl CpuTestHelper {
let mut data = 0;
for i in 0..4 {
if let Ok(pin) = self.cpu.get_pin(&format!("D{}", i)) {
let pin_guard = pin.lock();
if pin_guard.read() == PinValue::High {
data |= 1 << i;
if let Ok(pin_guard) = pin.lock() {
if pin_guard.read() == PinValue::High {
data |= 1 << i;
}
}
}
}
@ -172,8 +197,9 @@ impl CpuTestHelper {
fn tri_state_data_bus(&self) {
for i in 0..4 {
if let Ok(pin) = self.cpu.get_pin(&format!("D{}", i)) {
let mut pin_guard = pin.lock();
pin_guard.set_driver(Some("test".to_string()), PinValue::HighZ);
if let Ok(mut pin_guard) = pin.lock() {
pin_guard.set_driver(Some("test".to_string()), PinValue::HighZ);
}
}
}
}
@ -268,7 +294,7 @@ fn test_intel_4004_state_machine_progression() {
for i in 0..4 {
let pin_name = format!("D{}", i);
if let Ok(pin) = helper.cpu.get_pin(&pin_name) {
let mut pin_guard = pin.lock();
let mut pin_guard = pin.lock().unwrap();
pin_guard.set_driver(Some("test".to_string()), PinValue::High);
}
}
@ -326,6 +352,7 @@ fn test_intel_4004_reset_functionality() {
.get_pin("RESET")
.unwrap()
.lock()
.unwrap()
.set_driver(Some("test".to_string()), PinValue::High);
helper.cpu.update();
@ -335,6 +362,7 @@ fn test_intel_4004_reset_functionality() {
.get_pin("RESET")
.unwrap()
.lock()
.unwrap()
.set_driver(Some("test".to_string()), PinValue::Low);
// Process the reset signal for multiple cycles to ensure it's applied
@ -350,6 +378,7 @@ fn test_intel_4004_reset_functionality() {
.get_pin("RESET")
.unwrap()
.lock()
.unwrap()
.set_driver(Some("test".to_string()), PinValue::High);
helper.cpu.update();
thread::sleep(Duration::from_millis(1));

736
tests/intel_400x_tests.rs
View file

File diff suppressed because it is too large Load diff

52
tests/lib.rs
View file

@ -17,7 +17,6 @@ mod intel_400x_tests;
// Common test utilities and helpers
pub mod test_utils {
use std::sync::Arc;
use std::time::{Duration, Instant};
/// Create a deterministic time source for testing
@ -35,57 +34,6 @@ pub mod test_utils {
std::thread::sleep(duration);
}
/// Create a VirtualClock in MaxSpeed mode for fast deterministic tests.
///
/// The clock starts in stopped state. Call `clock.start()` after spawning
/// the governor thread.
///
/// # Parameters
/// - `tick_size_ns`: Virtual time advance per tick (default: 333ns for 750 kHz)
pub fn create_maxspeed_clock(tick_size_ns: u64) -> Arc<rusty_emu::virtual_clock::VirtualClock> {
let clock = Arc::new(rusty_emu::virtual_clock::VirtualClock::new(
Duration::from_nanos(tick_size_ns),
));
clock.set_mode(rusty_emu::virtual_clock::SimulationMode::MaxSpeed);
clock
}
/// Create a VirtualClock in SingleStep mode for precise state verification.
///
/// Each call to `clock.trigger_step()` advances virtual time by one tick.
pub fn create_singlestep_clock(tick_size_ns: u64) -> Arc<rusty_emu::virtual_clock::VirtualClock> {
let clock = Arc::new(rusty_emu::virtual_clock::VirtualClock::new(
Duration::from_nanos(tick_size_ns),
));
clock.set_mode(rusty_emu::virtual_clock::SimulationMode::SingleStep);
clock
}
/// Spawn a RealTimeGovernor thread for the given clock.
///
/// Returns a JoinHandle that can be used to wait for the governor to exit.
/// The governor will exit when `clock.stop()` is called.
pub fn spawn_governor(
clock: Arc<rusty_emu::virtual_clock::VirtualClock>,
) -> std::thread::JoinHandle<()> {
std::thread::spawn(move || {
let governor = rusty_emu::real_time_governor::RealTimeGovernor::with_defaults(clock);
governor.run();
})
}
/// Stop the virtual clock and wait for the governor thread to finish.
///
/// This ensures clean shutdown of the governor thread before the test ends.
pub fn stop_governor(
clock: &Arc<rusty_emu::virtual_clock::VirtualClock>,
handle: std::thread::JoinHandle<()>,
) {
clock.stop();
// Give the governor thread a moment to exit cleanly
let _ = handle.join();
}
/// Verify that a component implements all required traits
pub fn verify_intel400x_traits<C>(component: &C)
where

888
tests/virtual_time_tests.rs
View file

@ -1,888 +0,0 @@
//! Virtual Time Integration Tests
//!
//! Tests for the virtual time architecture (Phase 9):
//! - MaxSpeed mode for fast deterministic execution
//! - SingleStep mode for precise state verification
//! - Overclocking tests verifying component timing violations
//! - Virtual clock integration with ConfigurableSystem
use std::sync::Arc;
use std::time::Duration;
use rusty_emu::component::Component;
use rusty_emu::component_timing::ComponentTiming;
use rusty_emu::components::common::intel_400x::*;
use rusty_emu::components::memory::intel_4001::Intel4001;
use rusty_emu::components::memory::intel_4002::Intel4002;
use rusty_emu::components::memory::intel_4003::Intel4003;
use rusty_emu::real_time_governor::RealTimeGovernor;
use rusty_emu::system_config::SystemFactory;
use rusty_emu::virtual_clock::{SimulationMode, VirtualClock};
// =============================================================================
// MaxSpeed Mode Tests
// =============================================================================
#[cfg(test)]
mod maxspeed_tests {
use super::*;
/// Verify that a VirtualClock in MaxSpeed mode advances time
/// when driven by a RealTimeGovernor.
#[test]
fn test_maxspeed_clock_advances() {
let clock = Arc::new(VirtualClock::new(Duration::from_nanos(333)));
let governor = RealTimeGovernor::with_defaults(clock.clone());
let handle = std::thread::spawn(move || {
governor.run();
});
// Let the governor run for a bit (it calls clock.start() internally)
std::thread::sleep(Duration::from_millis(50));
// Virtual time should have advanced significantly
let vt = clock.now_ns();
assert!(vt > 0, "Virtual time should have advanced past 0");
// Verify we can read the time
assert!(clock.now() > Duration::ZERO, "Virtual time should be > 0");
clock.stop();
let _ = handle.join();
}
/// Verify that multiple time targets are reached in MaxSpeed mode.
#[test]
fn test_maxspeed_multiple_targets() {
let clock = Arc::new(VirtualClock::new(Duration::from_nanos(100)));
let governor = RealTimeGovernor::with_defaults(clock.clone());
let handle = std::thread::spawn(move || {
governor.run();
});
// Let the governor advance time
std::thread::sleep(Duration::from_millis(50));
// Virtual time should have advanced well past multiple targets
let vt = clock.now_ns();
assert!(vt >= 1000, "Should have passed 1000ns, got {}", vt);
assert!(vt >= 5000, "Should have passed 5000ns, got {}", vt);
assert!(vt >= 10000, "Should have passed 10000ns, got {}", vt);
clock.stop();
let _ = handle.join();
}
/// Verify that component update_at_time works with virtual time in MaxSpeed mode.
/// Tests that a ROM component can be updated with specific virtual times.
#[test]
fn test_maxspeed_component_update_at_time() {
let mut rom = Intel4001::new_with_access_time("TestROM".to_string(), 500);
// Load test data
rom.load_rom_data(vec![0xAB, 0xCD], 0).unwrap();
// Simulate address latching at virtual time T=0
rom.set_timing_state(TimingState::Idle);
rom.set_address_high_nibble(Some(0x0));
rom.set_address_low_nibble(Some(0x0));
rom.set_full_address_ready(true);
rom.set_address_latch_time(Some(Duration::ZERO));
// At T=0 (before access_time), data should not be ready
let timing = ComponentTiming::intel_4001();
let elapsed = Duration::ZERO;
assert!(
timing.check_access_time(elapsed).is_err(),
"Access time should not have elapsed at T=0"
);
// At T=500ns (exactly access_time), data should be ready
let elapsed_500 = Duration::from_nanos(500);
assert!(
timing.check_access_time(elapsed_500).is_ok(),
"Access time should have elapsed at T=500ns"
);
// At T=600ns (after access_time), data should definitely be ready
let elapsed_600 = Duration::from_nanos(600);
assert!(
timing.check_access_time(elapsed_600).is_ok(),
"Access time should have elapsed at T=600ns"
);
}
/// Verify that a ROM with 1ns access time works correctly through
/// the full state machine in MaxSpeed mode.
#[test]
fn test_maxspeed_rom_fast_access() {
// Create ROM with 1ns access time (fast for testing)
let mut rom = Intel4001::new_with_access_time("FastROM".to_string(), 1);
rom.load_rom_data(vec![0x42], 0).unwrap();
// Drive through state machine with virtual time
// T=0: Idle state
assert_eq!(rom.get_timing_state(), TimingState::Idle);
// T=100ns: Set address (simulating PHI1 rising edge)
let t = Duration::from_nanos(100);
rom.set_address_high_nibble(Some(0x0));
rom.set_address_low_nibble(Some(0x0));
rom.set_full_address_ready(true);
rom.set_address_latch_time(Some(t));
rom.set_timing_state(TimingState::AddressPhase);
assert_eq!(rom.get_timing_state(), TimingState::AddressPhase);
// T=200ns: Wait for access time (1ns already elapsed)
rom.set_timing_state(TimingState::WaitLatency);
// T=300ns: Drive data
rom.set_timing_state(TimingState::DriveData);
assert_eq!(rom.get_timing_state(), TimingState::DriveData);
// Verify data is accessible
assert_eq!(rom.read_rom(0x00).unwrap(), 0x42);
}
}
// =============================================================================
// SingleStep Mode Tests
// =============================================================================
#[cfg(test)]
mod singlestep_tests {
use super::*;
/// Verify that each trigger_step() advances virtual time by exactly one tick.
#[test]
fn test_singlestep_advances_one_tick() {
let clock = Arc::new(VirtualClock::new(Duration::from_nanos(333)));
clock.set_mode(SimulationMode::SingleStep);
let governor = RealTimeGovernor::with_defaults(clock.clone());
let handle = std::thread::spawn(move || {
governor.run();
});
// Wait for governor to start
std::thread::sleep(Duration::from_millis(50));
// Initial time should be 0
assert_eq!(clock.now_ns(), 0, "Initial time should be 0");
// Trigger one step
clock.trigger_step();
std::thread::sleep(Duration::from_millis(50));
assert_eq!(clock.now_ns(), 333, "After 1 step, time should be 333ns");
// Trigger another step
clock.trigger_step();
std::thread::sleep(Duration::from_millis(50));
assert_eq!(clock.now_ns(), 666, "After 2 steps, time should be 666ns");
// Trigger a third step
clock.trigger_step();
std::thread::sleep(Duration::from_millis(50));
assert_eq!(clock.now_ns(), 999, "After 3 steps, time should be 999ns");
clock.stop();
let _ = handle.join();
}
/// Verify that ROM state can be inspected at specific virtual times
/// using SingleStep mode.
#[test]
fn test_singlestep_rom_state_at_specific_time() {
let clock = Arc::new(VirtualClock::new(Duration::from_nanos(100)));
clock.set_mode(SimulationMode::SingleStep);
let governor = RealTimeGovernor::with_defaults(clock.clone());
let handle = std::thread::spawn(move || {
governor.run();
});
// Wait for governor to start
std::thread::sleep(Duration::from_millis(50));
// Create ROM with 500ns access time (standard Intel 4001)
let mut rom = Intel4001::new_with_access_time("StepROM".to_string(), 500);
rom.load_rom_data(vec![0xAB], 0).unwrap();
// Trigger 1 step → T=100ns — latch address
clock.trigger_step();
std::thread::sleep(Duration::from_millis(20));
let t_latch = clock.now();
assert!(t_latch >= Duration::from_nanos(100));
rom.set_address_latch_time(Some(t_latch));
rom.set_address_high_nibble(Some(0x0));
rom.set_address_low_nibble(Some(0x0));
rom.set_full_address_ready(true);
// At T=100ns, 0ns have elapsed since latch — access time NOT met
let timing = ComponentTiming::intel_4001();
assert!(
timing.check_access_time(Duration::ZERO).is_err(),
"At T=100ns (0ns since latch), access time (500ns) should NOT be met"
);
// Trigger 4 more steps → T=500ns (4 × 100ns = 400ns more)
for _ in 0..4 {
clock.trigger_step();
std::thread::sleep(Duration::from_millis(20));
}
// At T=500ns, 400ns have elapsed since latch at T=100ns — still NOT enough
let elapsed_400 = Duration::from_nanos(400);
assert!(
timing.check_access_time(elapsed_400).is_err(),
"At T=500ns (400ns since latch at T=100ns), access time (500ns) should NOT be met"
);
// Trigger 1 more step → T=600ns
clock.trigger_step();
std::thread::sleep(Duration::from_millis(20));
// At T=600ns, 500ns have elapsed since latch at T=100ns — exactly access time
let elapsed_500 = Duration::from_nanos(500);
assert!(
timing.check_access_time(elapsed_500).is_ok(),
"At T=600ns (500ns since latch at T=100ns), access time (500ns) SHOULD be met"
);
clock.stop();
let _ = handle.join();
}
/// Verify that trigger_step returns false when not in SingleStep mode.
#[test]
fn test_trigger_step_only_works_in_singlestep() {
let clock = Arc::new(VirtualClock::new(Duration::from_nanos(333)));
// Default mode is RealTime — trigger_step should fail
assert!(
!clock.trigger_step(),
"trigger_step should return false in RealTime mode"
);
// Switch to MaxSpeed — trigger_step should still fail
clock.set_mode(SimulationMode::MaxSpeed);
assert!(
!clock.trigger_step(),
"trigger_step should return false in MaxSpeed mode"
);
// Switch to SingleStep — now it should work
clock.set_mode(SimulationMode::SingleStep);
assert!(
clock.trigger_step(),
"trigger_step should return true in SingleStep mode"
);
}
/// Verify precise tick count tracking in SingleStep mode.
#[test]
fn test_singlestep_tick_count() {
let clock = Arc::new(VirtualClock::new(Duration::from_nanos(100)));
clock.set_mode(SimulationMode::SingleStep);
let governor = RealTimeGovernor::with_defaults(clock.clone());
let handle = std::thread::spawn(move || {
governor.run();
});
// Wait for governor to start
std::thread::sleep(Duration::from_millis(50));
assert_eq!(clock.tick_count(), 0, "Initial tick count should be 0");
// Trigger 5 steps
for _ in 0..5 {
clock.trigger_step();
std::thread::sleep(Duration::from_millis(20));
}
// After 5 ticks of 100ns each
assert_eq!(clock.now_ns(), 500, "After 5 steps, time should be 500ns");
assert_eq!(clock.tick_count(), 5, "After 5 steps, tick_count should be 5");
clock.stop();
let _ = handle.join();
}
}
// =============================================================================
// Overclocking Tests
// =============================================================================
#[cfg(test)]
mod overclocking_tests {
use super::*;
/// Verify that ROM (500ns access time) fails timing check at 2 MHz.
///
/// At 2 MHz, the clock phase is 250ns. The ROM needs 500ns from address
/// valid to data ready, but only gets 250ns — a timing violation.
#[test]
fn test_overclocking_rom_fails_at_2mhz() {
let rom_timing = ComponentTiming::intel_4001();
// 2 MHz clock → 500ns cycle → 250ns per phase
let phase_time = Duration::from_nanos(250);
// ROM has 500ns access time, but phase is only 250ns
assert!(
rom_timing.check_access_time(phase_time).is_err(),
"ROM (500ns access) should FAIL at 2 MHz (250ns phase)"
);
// Also verify: ROM does NOT support 2 MHz
assert!(
!rom_timing.supports_frequency(2_000_000.0),
"ROM should NOT support 2 MHz (max is 750 kHz)"
);
}
/// Verify that RAM (500ns access time) fails timing check at 2 MHz.
#[test]
fn test_overclocking_ram_fails_at_2mhz() {
let ram_timing = ComponentTiming::intel_4002();
// 2 MHz clock → 250ns per phase
let phase_time = Duration::from_nanos(250);
// RAM has 500ns access time, but phase is only 250ns
assert!(
ram_timing.check_access_time(phase_time).is_err(),
"RAM (500ns access) should FAIL at 2 MHz (250ns phase)"
);
assert!(
!ram_timing.supports_frequency(2_000_000.0),
"RAM should NOT support 2 MHz (max is 750 kHz)"
);
}
/// Verify that the shift register (200ns access time) STILL WORKS at 2 MHz.
///
/// The Intel 4003 has a faster 200ns access time, so at 2 MHz (250ns phase),
/// there's still enough time for data to become valid. This models real
/// hardware behavior where faster chips continue working when slower ones fail.
#[test]
fn test_shift_register_works_at_higher_frequency() {
let sr_timing = ComponentTiming::intel_4003();
// 2 MHz clock → 250ns per phase
let phase_time = Duration::from_nanos(250);
// Shift register has 200ns access time, phase is 250ns — PLENTY of time
assert!(
sr_timing.check_access_time(phase_time).is_ok(),
"Shift register (200ns access) should WORK at 2 MHz (250ns phase)"
);
// Shift register supports 1 MHz
assert!(
sr_timing.supports_frequency(1_000_000.0),
"Shift register should support 1 MHz"
);
// But NOT 2 MHz (max is 1 MHz)
assert!(
!sr_timing.supports_frequency(2_000_000.0),
"Shift register should NOT support 2 MHz (max is 1 MHz)"
);
// However, the access time check passes because 250ns > 200ns.
// This is the key insight: access_time and max_clock_frequency are
// independent constraints. The access time is met (250ns >= 200ns)
// even though the frequency exceeds the spec.
}
/// Verify the overclocking scenario from the timing architecture plan:
/// At 2 MHz, ROM and RAM fail while the shift register keeps working.
#[test]
fn test_overclocking_scenario_comprehensive() {
let rom_timing = ComponentTiming::intel_4001();
let ram_timing = ComponentTiming::intel_4002();
let sr_timing = ComponentTiming::intel_4003();
let cpu_timing = ComponentTiming::intel_4004();
// 2 MHz clock: phase = 250ns
let phase_time_2mhz = Duration::from_nanos(250);
// ROM: 500ns access, 250ns available → FAIL
assert!(rom_timing.check_access_time(phase_time_2mhz).is_err());
// RAM: 500ns access, 250ns available → FAIL
assert!(ram_timing.check_access_time(phase_time_2mhz).is_err());
// Shift register: 200ns access, 250ns available → OK
assert!(sr_timing.check_access_time(phase_time_2mhz).is_ok());
// CPU: 0ns access time → always OK (CPU doesn't have "access time")
assert!(cpu_timing.check_access_time(phase_time_2mhz).is_ok());
// Now at standard 750 kHz: phase = 666ns
let phase_time_750khz = Duration::from_nanos(666);
// All components should work at 750 kHz
assert!(rom_timing.check_access_time(phase_time_750khz).is_ok());
assert!(ram_timing.check_access_time(phase_time_750khz).is_ok());
assert!(sr_timing.check_access_time(phase_time_750khz).is_ok());
assert!(cpu_timing.check_access_time(phase_time_750khz).is_ok());
}
/// Verify that ComponentTiming::min_clock_period() returns correct values.
#[test]
fn test_min_clock_period_per_component() {
let rom_timing = ComponentTiming::intel_4001();
let ram_timing = ComponentTiming::intel_4002();
let sr_timing = ComponentTiming::intel_4003();
// ROM: max 750 kHz → min period ~1333ns
let rom_period = rom_timing.min_clock_period();
assert!(
rom_period > Duration::from_nanos(1300) && rom_period < Duration::from_nanos(1400),
"ROM min clock period should be ~1333ns, got {:?}",
rom_period
);
// RAM: max 750 kHz → min period ~1333ns
let ram_period = ram_timing.min_clock_period();
assert!(
ram_period > Duration::from_nanos(1300) && ram_period < Duration::from_nanos(1400),
"RAM min clock period should be ~1333ns, got {:?}",
ram_period
);
// Shift register: max 1 MHz → min period 1000ns
let sr_period = sr_timing.min_clock_period();
assert!(
sr_period > Duration::from_nanos(900) && sr_period < Duration::from_nanos(1100),
"Shift register min clock period should be ~1000ns, got {:?}",
sr_period
);
}
/// Verify setup time and hold time checks work correctly.
#[test]
fn test_setup_and_hold_time_checks() {
let rom_timing = ComponentTiming::intel_4001();
// Setup time: 100ns
assert!(rom_timing.check_setup_time(Duration::from_nanos(150)).is_ok());
assert!(rom_timing.check_setup_time(Duration::from_nanos(100)).is_ok());
assert!(rom_timing.check_setup_time(Duration::from_nanos(50)).is_err());
// Hold time: 50ns
assert!(rom_timing.check_hold_time(Duration::from_nanos(100)).is_ok());
assert!(rom_timing.check_hold_time(Duration::from_nanos(50)).is_ok());
assert!(rom_timing.check_hold_time(Duration::from_nanos(25)).is_err());
}
/// Verify that timing violations contain meaningful error information.
#[test]
fn test_timing_violation_error_details() {
let rom_timing = ComponentTiming::intel_4001();
let err = rom_timing.check_access_time(Duration::from_nanos(100));
assert!(err.is_err());
let err_msg = format!("{:?}", err.unwrap_err());
assert!(
err_msg.contains("Intel 4001 ROM") || err_msg.contains("4001"),
"Violation should mention component name: {}",
err_msg
);
}
}
// =============================================================================
// Virtual Clock Integration Tests
// =============================================================================
#[cfg(test)]
mod virtual_clock_integration_tests {
use super::*;
/// Verify that ConfigurableSystem creates and exposes a VirtualClock.
#[test]
fn test_configurable_system_creates_virtual_clock() {
let factory = SystemFactory::new();
let system = factory.create_from_json("configs/mcs4_basic.json").unwrap();
// The system should have a virtual clock
let clock = system.get_virtual_clock();
assert!(Arc::strong_count(clock) >= 1, "VirtualClock Arc should exist");
// Clock should have correct tick size for 750 kHz (333ns per quarter-cycle)
let tick_size = clock.tick_size();
assert!(
tick_size > Duration::ZERO,
"Tick size should be non-zero"
);
// For 750 kHz, cycle time is ~1333ns, quarter-cycle is ~333ns
assert_eq!(
tick_size,
Duration::from_nanos(333),
"Tick size should be 333ns for 750 kHz"
);
}
/// Verify that ConfigurableSystem's VirtualClock can be put in MaxSpeed mode.
#[test]
fn test_configurable_system_maxspeed_mode() {
let factory = SystemFactory::new();
let system = factory.create_from_json("configs/mcs4_basic.json").unwrap();
let clock = system.get_virtual_clock();
clock.set_mode(SimulationMode::MaxSpeed);
assert_eq!(clock.mode(), SimulationMode::MaxSpeed);
}
/// Verify that clock.stop() causes the governor thread to exit cleanly.
#[test]
fn test_virtual_clock_stop_exits_governor() {
let clock = Arc::new(VirtualClock::new(Duration::from_nanos(333)));
let governor = RealTimeGovernor::with_defaults(clock.clone());
let handle = std::thread::spawn(move || {
governor.run();
});
// Let the governor start and advance time
std::thread::sleep(Duration::from_millis(50));
assert!(clock.now_ns() > 0, "Clock should have advanced");
// Stop the clock
clock.stop();
// Governor thread should exit cleanly
let join_result = handle.join();
assert!(
join_result.is_ok(),
"Governor thread should exit cleanly after stop"
);
}
/// Verify that clock.stop() causes wait_until to return None.
#[test]
fn test_stop_unblocks_wait_until() {
let clock = Arc::new(VirtualClock::new(Duration::from_nanos(333)));
let governor = RealTimeGovernor::with_defaults(clock.clone());
let clock_clone = Arc::clone(&clock);
let handle = std::thread::spawn(move || {
governor.run();
});
// Let the governor start
std::thread::sleep(Duration::from_millis(50));
// Now stop the clock
clock.stop();
// wait_until for a far-future time should return None immediately
let result = clock_clone.wait_until(Duration::from_secs(100));
assert!(
result.is_none(),
"wait_until should return None after clock is stopped"
);
let _ = handle.join();
}
/// Verify pause/resume behavior: time stops advancing when paused.
#[test]
fn test_pause_resume_behavior() {
let clock = Arc::new(VirtualClock::new(Duration::from_nanos(333)));
let governor = RealTimeGovernor::with_defaults(clock.clone());
let handle = std::thread::spawn(move || {
governor.run();
});
// Let it run
std::thread::sleep(Duration::from_millis(50));
let time_before_pause = clock.now_ns();
assert!(time_before_pause > 0);
// Pause the clock
clock.pause();
assert!(clock.is_paused());
// Wait a short wall-clock time, then check virtual time hasn't advanced
std::thread::sleep(Duration::from_millis(50));
let time_after_pause = clock.now_ns();
// Virtual time should not have advanced significantly while paused
// (may have advanced by 1-2 ticks due to race, but not more)
let diff = time_after_pause.saturating_sub(time_before_pause);
assert!(
diff < 1000,
"Virtual time should not advance significantly while paused. \
Before: {}, After: {}, Diff: {}",
time_before_pause, time_after_pause, diff
);
// Resume the clock
clock.resume();
assert!(!clock.is_paused());
// Wait for time to advance again
std::thread::sleep(Duration::from_millis(50));
let time_after_resume = clock.now_ns();
assert!(
time_after_resume > time_after_pause,
"Virtual time should advance after resume"
);
clock.stop();
let _ = handle.join();
}
/// Verify that the VirtualClock reset works correctly.
#[test]
fn test_virtual_clock_reset() {
let clock = Arc::new(VirtualClock::new(Duration::from_nanos(333)));
let governor = RealTimeGovernor::with_defaults(clock.clone());
let handle = std::thread::spawn(move || {
governor.run();
});
// Advance time
std::thread::sleep(Duration::from_millis(50));
assert!(clock.now_ns() > 0);
// Stop and reset
clock.stop();
let _ = handle.join();
// Reset time to zero
clock.reset();
// Verify time is back to zero
assert_eq!(clock.now(), Duration::ZERO);
assert_eq!(clock.tick_count(), 0);
}
/// Verify speed multiplier can be changed dynamically.
#[test]
fn test_speed_multiplier_change() {
let clock = Arc::new(VirtualClock::new(Duration::from_nanos(333)));
// Default speed is 1.0x
assert!((clock.speed_multiplier() - 1.0).abs() < 0.001);
// Set to 0.5x
clock.set_speed_multiplier(0.5);
assert!((clock.speed_multiplier() - 0.5).abs() < 0.001);
// Set to 10.0x
clock.set_speed_multiplier(10.0);
assert!((clock.speed_multiplier() - 10.0).abs() < 0.01);
// Set to 0.001x (very slow)
clock.set_speed_multiplier(0.001);
assert!((clock.speed_multiplier() - 0.001).abs() < 0.0001);
}
/// Verify that has_reached works correctly for non-blocking time checks.
#[test]
fn test_has_reached_nonblocking() {
let clock = Arc::new(VirtualClock::new(Duration::from_nanos(100)));
let governor = RealTimeGovernor::with_defaults(clock.clone());
let handle = std::thread::spawn(move || {
governor.run();
});
// Initially, time is 0
assert!(clock.has_reached(Duration::ZERO));
assert!(!clock.has_reached(Duration::from_nanos(1)));
// Wait for time to advance
std::thread::sleep(Duration::from_millis(50));
// Now it should have reached various targets
assert!(clock.has_reached(Duration::from_nanos(100)));
assert!(clock.has_reached(Duration::from_nanos(1000)));
assert!(clock.has_reached(Duration::from_micros(5)));
clock.stop();
let _ = handle.join();
}
/// Verify tick_size can be changed dynamically.
#[test]
fn test_tick_size_change() {
let clock = Arc::new(VirtualClock::new(Duration::from_nanos(333)));
assert_eq!(clock.tick_size(), Duration::from_nanos(333));
clock.set_tick_size(Duration::from_nanos(100));
assert_eq!(clock.tick_size(), Duration::from_nanos(100));
clock.set_tick_size(Duration::from_nanos(500));
assert_eq!(clock.tick_size(), Duration::from_nanos(500));
}
}
// =============================================================================
// Component Timing with Virtual Time Tests
// =============================================================================
#[cfg(test)]
mod component_virtual_time_tests {
use super::*;
/// Verify that Intel4001 implements the timing() method correctly.
#[test]
fn test_intel4001_timing_profile() {
let rom = Intel4001::new("TestROM".to_string());
let timing = rom.timing();
assert_eq!(timing.name, "Intel 4001 ROM");
assert_eq!(timing.access_time, Duration::from_nanos(500));
assert_eq!(timing.propagation_delay, Duration::from_nanos(200));
assert_eq!(timing.setup_time, Duration::from_nanos(100));
assert_eq!(timing.hold_time, Duration::from_nanos(50));
assert!((timing.max_clock_frequency - 750_000.0).abs() < 1.0);
}
/// Verify that Intel4002 implements the timing() method correctly.
#[test]
fn test_intel4002_timing_profile() {
let ram = Intel4002::new("TestRAM".to_string());
let timing = ram.timing();
assert_eq!(timing.name, "Intel 4002 RAM");
assert_eq!(timing.access_time, Duration::from_nanos(500));
assert_eq!(timing.propagation_delay, Duration::from_nanos(200));
}
/// Verify that Intel4003 implements the timing() method correctly.
#[test]
fn test_intel4003_timing_profile() {
let sr = Intel4003::new("TestSR".to_string());
let timing = sr.timing();
assert_eq!(timing.name, "Intel 4003 Shift Register");
assert_eq!(timing.access_time, Duration::from_nanos(200));
assert_eq!(timing.propagation_delay, Duration::from_nanos(100));
assert!((timing.max_clock_frequency - 1_000_000.0).abs() < 1.0);
}
/// Verify that update_at_time() works correctly for ROM component.
/// This tests the virtual-time-aware update path.
#[test]
fn test_rom_update_at_time() {
let mut rom = Intel4001::new_with_access_time("TestROM".to_string(), 1);
rom.load_rom_data(vec![0x42], 0).unwrap();
rom.set_running(true);
// Call update_at_time at various virtual times
// This should work without panicking
rom.update_at_time(Duration::from_nanos(0));
rom.update_at_time(Duration::from_nanos(333));
rom.update_at_time(Duration::from_nanos(666));
rom.update_at_time(Duration::from_nanos(999));
// Component should still function correctly
assert_eq!(rom.read_rom(0x00).unwrap(), 0x42);
}
/// Verify that update_at_time() works correctly for RAM component.
#[test]
fn test_ram_update_at_time() {
let mut ram = Intel4002::new("TestRAM".to_string());
ram.set_running(true);
// Call update_at_time at various virtual times
rom_update_at_time_helper(&mut ram);
}
fn rom_update_at_time_helper(ram: &mut Intel4002) {
ram.update_at_time(Duration::from_nanos(0));
ram.update_at_time(Duration::from_nanos(333));
ram.update_at_time(Duration::from_nanos(666));
}
/// Verify that update_at_time() works correctly for shift register component.
#[test]
fn test_sr_update_at_time() {
let mut sr = Intel4003::new("TestSR".to_string());
sr.set_running(true);
// Call update_at_time at various virtual times
sr.update_at_time(Duration::from_nanos(0));
sr.update_at_time(Duration::from_nanos(333));
sr.update_at_time(Duration::from_nanos(666));
// Should not panic
}
/// Test that address latch time tracking works with virtual time.
#[test]
fn test_address_latch_time_virtual_time() {
let mut rom = Intel4001::new_with_access_time("TestROM".to_string(), 500);
// Set address latch time to a specific virtual time
let latch_time = Duration::from_nanos(1000);
rom.set_address_latch_time(Some(latch_time));
assert_eq!(rom.get_address_latch_time(), Some(latch_time));
// Clear it
rom.set_address_latch_time(None);
assert_eq!(rom.get_address_latch_time(), None);
}
/// Verify that the timing state machine works correctly with virtual time.
#[test]
fn test_timing_state_machine_with_virtual_time() {
let mut rom = Intel4001::new_with_access_time("TestROM".to_string(), 500);
// Start in Idle
assert_eq!(rom.get_timing_state(), TimingState::Idle);
// Simulate a complete memory access cycle with virtual time
let t0 = Duration::ZERO; // Start
let _t1 = Duration::from_nanos(333); // Address phase
let _t2 = Duration::from_nanos(666); // Wait latency
let t3 = Duration::from_nanos(999); // Drive data
// T0: Idle
rom.update_at_time(t0);
assert_eq!(rom.get_timing_state(), TimingState::Idle);
// T1: Address latched
let t1 = Duration::from_nanos(333);
rom.set_address_latch_time(Some(t1));
rom.set_timing_state(TimingState::AddressPhase);
assert_eq!(rom.get_timing_state(), TimingState::AddressPhase);
// T2: Waiting for access time
rom.set_timing_state(TimingState::WaitLatency);
assert_eq!(rom.get_timing_state(), TimingState::WaitLatency);
// T3: Access time (666ns) > 500ns → data ready
let elapsed = t3.saturating_sub(t1);
let timing = ComponentTiming::intel_4001();
assert!(
timing.check_access_time(elapsed).is_ok(),
"After 666ns, access time (500ns) should be met"
);
rom.set_timing_state(TimingState::DriveData);
assert_eq!(rom.get_timing_state(), TimingState::DriveData);
// Return to idle
rom.set_timing_state(TimingState::Idle);
assert_eq!(rom.get_timing_state(), TimingState::Idle);
}
}