Jan-Peter von Hunnius
6a335a15d4
Overhaul the Intel 4004 instruction set to match the real opcode map, adding missing instructions (NOP, FIM, FIN, JIN, ISZ, KBP, DCL, WR0-3, RD0-3) and refining two-byte instruction handling with proper M1/M2 data phases. Rewrite the CPU fetch-execute cycle to correctly process two-byte opcodes across separate clock cycles. Improve Intel 4001 ROM timing with M1/M2 nibble phase tracking and an A3 wait counter so the ROM drives data only when the CPU expects it. Fix state-machine transition helpers in Intel 4002 and 4003 to capture the old state before processing events, preventing incorrect exit/entry callbacks. Add non-propagating pin driver methods to prevent deadlocks caused by bidirectional pin connections during signal propagation. Add Fibonacci integration test and opcode fix plan document. Update all README files to reflect the new instruction set.
381 lines
13 KiB
Rust
381 lines
13 KiB
Rust
use std::thread;
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use std::time::Duration;
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use rusty_emu::component::Component;
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use rusty_emu::components::common::intel_400x::{Intel400xTimingState, TimingState};
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use rusty_emu::components::memory::intel_4001::Intel4001;
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use rusty_emu::pin::PinValue;
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/// Test to verify that Intel 4001 ROM unified state machine progresses correctly
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/// This test isolates unified state machine logic to verify proper state transitions
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#[test]
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fn test_intel_4001_state_machine_progression() {
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let mut rom = Intel4001::new_with_access_time("StateMachineTestROM".to_string(), 1); // 1ns for fast testing
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// Load test data: address 0x12 should contain 0xAB
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let test_data = vec![0x00; 0x12]; // Initialize with zeros
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let mut data_with_test = test_data;
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data_with_test.push(0xAB); // Add 0xAB at address 0x12
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rom.load_rom_data(data_with_test, 0).unwrap();
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// Get pin references for simulation
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let sync_pin = rom.get_pin("SYNC").unwrap();
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let cm_pin = rom.get_pin("CM").unwrap();
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let ci_pin = rom.get_pin("CI").unwrap();
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let phi1_pin = rom.get_pin("PHI1").unwrap();
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let phi2_pin = rom.get_pin("PHI2").unwrap();
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let reset_pin = rom.get_pin("RESET").unwrap();
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// Data pins for address and data verification
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let d0_pin = rom.get_pin("D0").unwrap();
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let d1_pin = rom.get_pin("D1").unwrap();
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let d2_pin = rom.get_pin("D2").unwrap();
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let d3_pin = rom.get_pin("D3").unwrap();
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// Start component
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rom.base.set_running(true);
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assert!(rom.is_running());
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// Initialize clock pins to Low
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{
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let mut phi1_guard = phi1_pin.lock();
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let mut phi2_guard = phi2_pin.lock();
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phi1_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
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phi2_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
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}
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// Initialize control pins
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// Note: RESET is active LOW, so set it to High to ensure component is not in reset
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{
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let mut sync_guard = sync_pin.lock();
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let mut cm_guard = cm_pin.lock();
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let mut ci_guard = ci_pin.lock();
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let mut reset_guard = reset_pin.lock();
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sync_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
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cm_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
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ci_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
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reset_guard.set_driver(Some("TEST".to_string()), PinValue::High); // Not in reset
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}
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// Initialize data pins to Low
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{
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let mut d0_guard = d0_pin.lock();
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let mut d1_guard = d1_pin.lock();
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let mut d2_guard = d2_pin.lock();
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let mut d3_guard = d3_pin.lock();
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d0_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
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d1_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
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d2_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
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d3_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
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}
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// Update to initialize clock states
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rom.update();
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// Verify initial state
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assert_eq!(rom.get_timing_state(), TimingState::Idle);
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println!("Initial state: {:?}", rom.get_timing_state());
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// Set up memory read operation: SYNC=1, CM=1, CI=0 (memory access)
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{
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let mut sync_guard = sync_pin.lock();
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let mut cm_guard = cm_pin.lock();
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let mut ci_guard = ci_pin.lock();
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sync_guard.set_driver(Some("TEST".to_string()), PinValue::High);
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cm_guard.set_driver(Some("TEST".to_string()), PinValue::High);
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ci_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Memory access
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}
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// Set up address high nibble (0x1 for address 0x12)
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{
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let mut d0_guard = d0_pin.lock();
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let mut d1_guard = d1_pin.lock();
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let mut d2_guard = d2_pin.lock();
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let mut d3_guard = d3_pin.lock();
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// 0x1 = 0001 (D0=1, D1=0, D2=0, D3=0)
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d0_guard.set_driver(Some("TEST".to_string()), PinValue::High);
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d1_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
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d2_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
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d3_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
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}
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// Wait for pins to settle
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thread::sleep(Duration::from_millis(1));
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// Trigger Φ1 rising edge to start memory operation and latch high nibble
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{
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let mut phi1_guard = phi1_pin.lock();
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phi1_guard.set_driver(Some("TEST".to_string()), PinValue::High);
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}
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// Update to process Φ1 rising edge
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rom.update();
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// Should have started memory operation and transitioned to AddressPhase
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assert_eq!(rom.get_timing_state(), TimingState::AddressPhase);
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println!(
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"State after Φ1 rising (high nibble): {:?}",
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rom.get_timing_state()
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);
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// Reset Φ1 to Low
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{
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let mut phi1_guard = phi1_pin.lock();
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phi1_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
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}
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// Update to process Φ1 falling edge
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rom.update();
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// Set up address low nibble (0x2 for address 0x12)
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{
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let mut d0_guard = d0_pin.lock();
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let mut d1_guard = d1_pin.lock();
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let mut d2_guard = d2_pin.lock();
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let mut d3_guard = d3_pin.lock();
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// 0x2 = 0010 (D0=0, D1=1, D2=0, D3=0)
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d0_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
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d1_guard.set_driver(Some("TEST".to_string()), PinValue::High);
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d2_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
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d3_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
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}
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// Wait for pins to settle
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thread::sleep(Duration::from_millis(1));
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// Trigger Φ1 rising edge again - ROM latches low nibble on PHI1 rising edge
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// (address nibbles are latched on Φ1 RISING edge, same as CPU drives address)
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{
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let mut phi1_guard = phi1_pin.lock();
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phi1_guard.set_driver(Some("TEST".to_string()), PinValue::High);
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}
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// Update to process Φ1 rising edge
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rom.update();
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// Should have latched low nibble and transitioned to WaitLatency
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// (both nibbles latched on successive PHI1 rising edges)
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let state_after_low_nibble = rom.get_timing_state();
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assert!(
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state_after_low_nibble == TimingState::WaitLatency,
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"Expected WaitLatency after latching both nibbles on PHI1 rising, got {:?}",
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state_after_low_nibble
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);
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println!(
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"State after second Φ1 rising (both nibbles latched): {:?}",
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state_after_low_nibble
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);
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// Remove test drivers from data pins to allow ROM to drive bus
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{
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let mut d0_guard = d0_pin.lock();
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let mut d1_guard = d1_pin.lock();
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let mut d2_guard = d2_pin.lock();
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let mut d3_guard = d3_pin.lock();
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d0_guard.remove_driver("TEST");
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d1_guard.remove_driver("TEST");
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d2_guard.remove_driver("TEST");
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d3_guard.remove_driver("TEST");
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}
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// ROM is in WaitLatency with a3_wait_cycles=1.
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// Need to cycle the clock to get through the wait period and into DriveData.
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// The ROM expects PHI2 rising edges to decrement a3_wait_cycles and transition.
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// Step 1: PHI1 falling + PHI2 rising (decrements a3_wait_cycles to 0)
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{
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let mut phi1_guard = phi1_pin.lock();
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phi1_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
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}
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{
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let mut phi2_guard = phi2_pin.lock();
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phi2_guard.set_driver(Some("TEST".to_string()), PinValue::High);
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}
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rom.update();
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// a3_wait_cycles decremented from 1 to 0
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// Step 2: PHI2 falling + PHI1 rising (no transition yet, just clock edge)
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{
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let mut phi2_guard = phi2_pin.lock();
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phi2_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
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}
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{
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let mut phi1_guard = phi1_pin.lock();
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phi1_guard.set_driver(Some("TEST".to_string()), PinValue::High);
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}
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rom.update();
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// Step 3: PHI1 falling + PHI2 rising (a3_wait_cycles=0, transitions to DriveData)
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{
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let mut phi1_guard = phi1_pin.lock();
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phi1_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
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}
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{
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let mut phi2_guard = phi2_pin.lock();
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phi2_guard.set_driver(Some("TEST".to_string()), PinValue::High);
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}
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rom.update();
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// Should now be in DriveData (process_latency_elapsed on this PHI2 rising)
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// But return statement means data isn't driven yet
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// Step 4: PHI2 falling + PHI1 rising
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{
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let mut phi2_guard = phi2_pin.lock();
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phi2_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
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}
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{
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let mut phi1_guard = phi1_pin.lock();
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phi1_guard.set_driver(Some("TEST".to_string()), PinValue::High);
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}
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rom.update();
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// Step 5: PHI1 falling + PHI2 rising - NOW ROM drives data
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{
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let mut phi1_guard = phi1_pin.lock();
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phi1_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
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}
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{
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let mut phi2_guard = phi2_pin.lock();
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phi2_guard.set_driver(Some("TEST".to_string()), PinValue::High);
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}
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rom.update();
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// Should be in DriveData and driving OPR (high nibble of 0xAB = 0xA)
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assert_eq!(rom.get_timing_state(), TimingState::DriveData);
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println!("State after PHI2 rising (driving data): {:?}", rom.get_timing_state());
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// Wait for pins to settle after ROM drives data
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thread::sleep(Duration::from_millis(1));
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// Verify OPR is being driven on the bus
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// Data 0xAB has high nibble 0xA = 1010 (D0=0, D1=1, D2=0, D3=1)
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assert_eq!(d0_pin.lock().read(), PinValue::Low, "D0 should be Low for 0xA");
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assert_eq!(d1_pin.lock().read(), PinValue::High, "D1 should be High for 0xA");
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assert_eq!(d2_pin.lock().read(), PinValue::Low, "D2 should be Low for 0xA");
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assert_eq!(d3_pin.lock().read(), PinValue::High, "D3 should be High for 0xA");
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println!("OPR data verified: 0xA");
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}
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/// Test to verify that unified state machine doesn't progress without proper control signals
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#[test]
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fn test_intel_4001_state_machine_no_progression_without_signals() {
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let mut rom = Intel4001::new_with_access_time("NoProgressionTestROM".to_string(), 1);
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// Get pin references for simulation
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let phi1_pin = rom.get_pin("PHI1").unwrap();
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let phi2_pin = rom.get_pin("PHI2").unwrap();
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// Start component
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rom.base.set_running(true);
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assert!(rom.is_running());
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// Initialize clock pins to Low
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{
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let mut phi1_guard = phi1_pin.lock();
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let mut phi2_guard = phi2_pin.lock();
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phi1_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
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phi2_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
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}
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// Update to initialize clock states
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rom.update();
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// Verify initial state
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assert_eq!(rom.get_timing_state(), TimingState::Idle);
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// Trigger clock edges without setting up control signals
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{
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let mut phi1_guard = phi1_pin.lock();
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phi1_guard.set_driver(Some("TEST".to_string()), PinValue::High);
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}
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// Update to process Φ1 rising edge
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rom.update();
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// Should still be in Idle state since control signals are not set
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assert_eq!(rom.get_timing_state(), TimingState::Idle);
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// Reset Φ1 to Low
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{
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let mut phi1_guard = phi1_pin.lock();
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phi1_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
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}
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// Update to process Φ1 falling edge
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rom.update();
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// Trigger Φ2 rising edge
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{
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let mut phi2_guard = phi2_pin.lock();
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phi2_guard.set_driver(Some("TEST".to_string()), PinValue::High);
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}
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// Update to process Φ2 rising edge
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rom.update();
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// Should still be in Idle state
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assert_eq!(rom.get_timing_state(), TimingState::Idle);
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}
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/// Test to verify that reset properly clears unified state machine
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#[test]
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fn test_intel_4001_state_machine_reset() {
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let mut rom = Intel4001::new_with_access_time("ResetTestROM".to_string(), 1);
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// Get pin references for simulation
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let sync_pin = rom.get_pin("SYNC").unwrap();
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let cm_pin = rom.get_pin("CM").unwrap();
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let ci_pin = rom.get_pin("CI").unwrap();
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let phi1_pin = rom.get_pin("PHI1").unwrap();
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let reset_pin = rom.get_pin("RESET").unwrap();
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// Start component
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rom.base.set_running(true);
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assert!(rom.is_running());
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// Initialize clock pins to Low
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{
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let mut phi1_guard = phi1_pin.lock();
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phi1_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
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}
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// Update to initialize clock states
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rom.update();
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// Verify initial state
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assert_eq!(rom.get_timing_state(), TimingState::Idle);
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// Set up memory read operation: SYNC=1, CM=1, CI=0 (memory access)
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{
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let mut sync_guard = sync_pin.lock();
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let mut cm_guard = cm_pin.lock();
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let mut ci_guard = ci_pin.lock();
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sync_guard.set_driver(Some("TEST".to_string()), PinValue::High);
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cm_guard.set_driver(Some("TEST".to_string()), PinValue::High);
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ci_guard.set_driver(Some("TEST".to_string()), PinValue::Low); // Memory access
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}
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// Trigger Φ1 rising edge to start memory operation
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{
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let mut phi1_guard = phi1_pin.lock();
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phi1_guard.set_driver(Some("TEST".to_string()), PinValue::High);
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}
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// Update to process Φ1 rising edge
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rom.update();
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// Should have started memory operation and transitioned to AddressPhase
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assert_eq!(rom.get_timing_state(), TimingState::AddressPhase);
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// Assert RESET (active LOW - set to Low to trigger reset)
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{
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let mut reset_guard = reset_pin.lock();
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reset_guard.set_driver(Some("TEST".to_string()), PinValue::Low);
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}
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// Update to process reset
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rom.update();
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// Should have returned to Idle state
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assert_eq!(rom.get_timing_state(), TimingState::Idle);
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}
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