167 lines
No EOL
4 KiB
JSON
167 lines
No EOL
4 KiB
JSON
{
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"name": "IntelMcs4Max",
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"description": "Fig.1 MCS-4 System with 16 ROMs and 16 RAMs",
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"version": "1.0",
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"metadata": {
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"configuration": "fig1",
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"rom_count": 16,
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"ram_count": 16,
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"shift_register_count": 3,
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"cpu_speed": 750000,
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"architecture": "mcs4_max"
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},
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"components": {
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"cpu": {
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"single": {
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"component_type": "intel_4004",
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"name": "CPU_4004",
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"properties": {
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"clock_speed": 750000
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}
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}
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},
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"clock": {
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"single": {
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"component_type": "generic_clock",
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"name": "SYSTEM_CLOCK",
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"properties": {
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"frequency": 750000
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}
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}
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},
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"roms": {
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"array": {
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"component_type": "intel_4001",
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"count": 16,
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"naming_pattern": "ROM_4001_{:02}",
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"properties": {}
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}
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},
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"rams": {
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"array": {
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"component_type": "intel_4002",
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"count": 16,
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"naming_pattern": "RAM_4002_{:02}",
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"properties": {
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"variant": "Type1",
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"access_time": 500
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},
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"overrides": {
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"03": {
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"variant": "Type2"
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}
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}
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}
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},
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"shift_registers": {
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"array": {
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"component_type": "intel_4003",
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"count": 3,
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"names": [
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"SHIFT_4003_ROM15",
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"SHIFT_4003_RAM3_1",
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"SHIFT_4003_RAM3_2"
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],
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"properties": {}
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}
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}
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},
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"connections": {
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"clock_signals": {
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"connection_type": "clock",
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"source": {
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"component": "clock",
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"pin": "CLK"
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},
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"targets": [
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{"component": "cpu", "pin": "PHI1"},
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{"component": "cpu", "pin": "PHI2"}
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]
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},
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"rom_clock_signals": {
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"connection_type": "clock_fanout",
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"source": {
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"component": "clock",
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"pin": "CLK"
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},
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"target_pattern": {
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"component_pattern": "ROM_4001_{:02}",
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"pins": ["PHI1", "PHI2"]
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}
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},
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"ram_clock_signals": {
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"connection_type": "clock_fanout",
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"source": {
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"component": "clock",
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"pin": "CLK"
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},
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"target_pattern": {
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"component_pattern": "RAM_4002_{:02}",
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"pins": ["PHI1", "PHI2"]
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}
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},
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"shift_clock_signals": {
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"connection_type": "clock_fanout",
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"source": {
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"component": "clock",
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"pin": "CLK"
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},
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"target_pattern": {
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"component_pattern": "SHIFT_4003_ROM15",
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"pins": ["PHI1", "PHI2"]
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}
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},
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"shift_ram3_clock_signals": {
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"connection_type": "clock_fanout",
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"source": {
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"component": "clock",
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"pin": "CLK"
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},
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"targets": [
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{"component": "SHIFT_4003_RAM3_1", "pin": "PHI1"},
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{"component": "SHIFT_4003_RAM3_1", "pin": "PHI2"},
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{"component": "SHIFT_4003_RAM3_2", "pin": "PHI1"},
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{"component": "SHIFT_4003_RAM3_2", "pin": "PHI2"}
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]
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},
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"rom15_shift_register": {
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"connection_type": "io_chain",
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"source_component": "ROM_4001_15",
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"source_pins": ["IO0", "IO1", "IO2", "IO3"],
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"target_component": "SHIFT_4003_ROM15",
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"target_pins": ["D0", "D1", "D2", "D3"]
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},
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"ram3_shift_chain": {
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"connection_type": "serial_chain",
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"stages": [
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{
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"source_component": "RAM_4002_03",
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"source_pins": ["O0", "O1", "O2", "O3"],
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"target_component": "SHIFT_4003_RAM3_1",
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"target_pins": ["D0", "D1", "D2", "D3"]
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},
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{
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"source_component": "SHIFT_4003_RAM3_1",
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"source_pins": ["O0", "O1", "O2", "O3"],
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"target_component": "SHIFT_4003_RAM3_2",
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"target_pins": ["D0", "D1", "D2", "D3"]
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}
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]
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}
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},
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"layout": {
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"grid_size": [20, 20],
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"positions": {
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"cpu": [1, 1],
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"clock": [0, 0],
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"ROM_4001_00": [2, 0],
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"ROM_4001_15": [17, 0],
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"RAM_4002_00": [2, 2],
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"RAM_4002_03": [5, 2],
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"RAM_4002_15": [17, 2],
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"SHIFT_4003_ROM15": [18, 0],
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"SHIFT_4003_RAM3_1": [6, 2],
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"SHIFT_4003_RAM3_2": [7, 2]
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}
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}
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} |