362 lines
14 KiB
Rust
362 lines
14 KiB
Rust
//! Integration tests for Intel 400x common functionality
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//!
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//! These tests verify that concrete implementations correctly use
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//! the intel_400x traits and that the common functionality works
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//! as expected in real usage scenarios.
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use rusty_emu::component::Component;
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use rusty_emu::components::common::intel_400x::*;
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use rusty_emu::components::memory::intel_4001::Intel4001;
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use rusty_emu::pin::PinValue;
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use std::time::Duration;
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#[cfg(test)]
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mod intel_4001_integration_tests {
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use super::*;
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#[test]
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fn test_intel4001_uses_common_traits() {
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let rom = Intel4001::new("ROM_4001".to_string());
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// Verify that Intel4001 implements all the common traits
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// These should compile without errors if the trait implementations are correct
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// Test Intel400xClockHandling trait
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let _: &dyn Intel400xClockHandling = &rom;
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// Test Intel400xDataBus trait
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let _: &dyn Intel400xDataBus = &rom;
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// Test Intel400xAddressHandling trait
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let _: &dyn Intel400xAddressHandling = &rom;
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// Test Intel400xControlPins trait
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let _: &dyn Intel400xControlPins = &rom;
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// Test Intel400xResetHandling trait
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let _: &dyn Intel400xResetHandling = &rom;
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// Test Intel400xTimingState trait
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let _: &dyn Intel400xTimingState = &rom;
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// Verify the component has the expected name
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assert_eq!(rom.name(), "ROM_4001");
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}
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#[test]
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fn test_intel4001_timing_state_integration() {
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let mut rom = Intel4001::new_with_access_time("ROM_4001".to_string(), 1);
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// Test that timing state works correctly with the trait
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let initial_state: TimingState = rom.get_timing_state();
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assert_eq!(initial_state, TimingState::Idle);
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// Test state changes through the trait
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rom.set_timing_state(TimingState::AddressPhase);
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let address_state: TimingState = rom.get_timing_state();
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assert_eq!(address_state, TimingState::AddressPhase);
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rom.set_timing_state(TimingState::WaitLatency);
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let wait_state: TimingState = rom.get_timing_state();
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assert_eq!(wait_state, TimingState::WaitLatency);
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rom.set_timing_state(TimingState::DriveData);
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let drive_state: TimingState = rom.get_timing_state();
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assert_eq!(drive_state, TimingState::DriveData);
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}
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#[test]
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fn test_intel4001_address_handling_integration() {
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let mut rom = Intel4001::new_with_access_time("ROM_4001".to_string(), 1);
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// Test address handling through the trait
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rom.set_address_high_nibble(Some(0x12));
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rom.set_address_low_nibble(Some(0x34));
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rom.set_full_address_ready(true);
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// Verify the values are accessible through the trait
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assert_eq!(rom.get_address_high_nibble(), Some(0x12));
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assert_eq!(rom.get_address_low_nibble(), Some(0x34));
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assert_eq!(rom.get_full_address_ready(), true);
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// Test access time configuration
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assert_eq!(rom.get_access_time(), 1);
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// Test address latch time handling
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let test_time = std::time::Instant::now();
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rom.set_address_latch_time(Some(test_time));
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assert_eq!(rom.get_address_latch_time(), Some(test_time));
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}
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#[test]
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fn test_common_functionality_with_real_component() {
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let mut rom = Intel4001::new_with_access_time("ROM_4001".to_string(), 1);
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// Test that common functionality works with the real component
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let test_data = vec![0xAB, 0xCD];
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rom.load_rom_data(test_data, 0).unwrap();
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// Test direct memory access (bypassing the pin interface)
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assert_eq!(rom.read_rom(0x00).unwrap(), 0xAB);
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assert_eq!(rom.read_rom(0x01).unwrap(), 0xCD);
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// Test that the component maintains its state correctly
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assert_eq!(rom.get_rom_size(), 256);
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assert_eq!(rom.get_access_time(), 1);
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}
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#[test]
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fn test_timing_constants_usage() {
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// Test that timing constants are used appropriately
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let fast_rom = Intel4001::new_with_access_time(
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"FAST_ROM".to_string(),
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TimingConstants::FAST_ACCESS_TIME.as_nanos() as u64,
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);
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let default_rom = Intel4001::new_with_access_time(
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"DEFAULT_ROM".to_string(),
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TimingConstants::DEFAULT_ACCESS_TIME.as_nanos() as u64,
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);
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assert_eq!(
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fast_rom.get_access_time(),
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TimingConstants::FAST_ACCESS_TIME.as_nanos() as u64
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);
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assert_eq!(
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default_rom.get_access_time(),
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TimingConstants::DEFAULT_ACCESS_TIME.as_nanos() as u64
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);
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assert!(TimingConstants::FAST_ACCESS_TIME < TimingConstants::DEFAULT_ACCESS_TIME);
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assert!(TimingConstants::ADDRESS_SETUP > Duration::from_nanos(0));
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assert!(TimingConstants::DATA_VALID > Duration::from_nanos(0));
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}
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#[test]
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fn test_state_machine_integration() {
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let mut rom = Intel4001::new_with_access_time("ROM_4001".to_string(), 1);
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// Test state machine progression through the trait interface
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assert_eq!(rom.get_timing_state(), TimingState::Idle);
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// Progress through states
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rom.set_timing_state(TimingState::AddressPhase);
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assert_eq!(rom.get_timing_state(), TimingState::AddressPhase);
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rom.set_timing_state(TimingState::WaitLatency);
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assert_eq!(rom.get_timing_state(), TimingState::WaitLatency);
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rom.set_timing_state(TimingState::DriveData);
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assert_eq!(rom.get_timing_state(), TimingState::DriveData);
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// Return to idle
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rom.set_timing_state(TimingState::Idle);
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assert_eq!(rom.get_timing_state(), TimingState::Idle);
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}
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#[test]
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fn test_address_latching_integration() {
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let mut rom = Intel4001::new_with_access_time("ROM_4001".to_string(), 1);
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// Test address latching through the trait
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rom.set_address_high_nibble(Some(0x0F));
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rom.set_address_low_nibble(Some(0x23));
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rom.set_full_address_ready(true);
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// Verify the address was assembled correctly
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assert_eq!(rom.get_address_high_nibble(), Some(0x0F));
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assert_eq!(rom.get_address_low_nibble(), Some(0x23));
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assert_eq!(rom.get_full_address_ready(), true);
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// Test clearing the address
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rom.set_address_high_nibble(None);
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rom.set_address_low_nibble(None);
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rom.set_full_address_ready(false);
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assert_eq!(rom.get_address_high_nibble(), None);
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assert_eq!(rom.get_address_low_nibble(), None);
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assert_eq!(rom.get_full_address_ready(), false);
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}
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#[test]
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fn test_multiple_component_interaction() {
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// Test how multiple components using the same traits interact
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let rom1 = Intel4001::new_with_access_time("ROM1".to_string(), 1);
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let rom2 = Intel4001::new_with_access_time("ROM2".to_string(), 2);
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// Both should implement the same traits
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let _: &dyn Intel400xClockHandling = &rom1;
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let _: &dyn Intel400xClockHandling = &rom2;
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let _: &dyn Intel400xDataBus = &rom1;
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let _: &dyn Intel400xDataBus = &rom2;
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// They should have different access times
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assert_eq!(rom1.get_access_time(), 1);
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assert_eq!(rom2.get_access_time(), 2);
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// Both should start in the same initial state
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assert_eq!(rom1.get_timing_state(), TimingState::Idle);
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assert_eq!(rom2.get_timing_state(), TimingState::Idle);
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}
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#[test]
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fn test_performance_characteristics() {
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// Test that the common functionality maintains expected performance characteristics
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let mut rom = Intel4001::new_with_access_time("ROM_4001".to_string(), 1);
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// Test that access time is correctly configured
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assert_eq!(rom.get_access_time(), 1);
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// Test that the component can handle rapid state changes
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for _ in 0..100 {
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rom.set_timing_state(TimingState::Idle);
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rom.set_timing_state(TimingState::AddressPhase);
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rom.set_timing_state(TimingState::WaitLatency);
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rom.set_timing_state(TimingState::DriveData);
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}
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// Should end up in the expected final state
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assert_eq!(rom.get_timing_state(), TimingState::DriveData);
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}
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#[test]
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fn test_memory_operation_simulation() {
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let mut rom = Intel4001::new_with_access_time("ROM_4001".to_string(), 1);
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// Load test data
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let test_data = vec![0x12, 0x34, 0x56, 0x78];
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rom.load_rom_data(test_data.clone(), 0).unwrap();
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// Test that the ROM correctly stores and retrieves data
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for (i, &expected) in test_data.iter().enumerate() {
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assert_eq!(rom.read_rom(i as u8).unwrap(), expected);
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}
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// Test that the component maintains correct metadata
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assert_eq!(rom.get_rom_size(), 256);
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assert_eq!(rom.get_access_time(), 1);
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assert_eq!(rom.name(), "ROM_4001");
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}
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#[test]
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fn test_trait_consistency_across_implementations() {
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// Test that different components implement the traits consistently
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let rom = Intel4001::new_with_access_time("ROM_4001".to_string(), 1);
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// Test that all trait methods are available and work consistently
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let base_component: &dyn Component = &rom;
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assert_eq!(base_component.name(), "ROM_4001");
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// Test that timing state trait works
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let timing_state: &dyn Intel400xTimingState = &rom;
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assert_eq!(timing_state.get_timing_state(), TimingState::Idle);
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assert_eq!(timing_state.get_access_time(), Duration::from_nanos(1));
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// Test that clock handling trait works
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let clock_handler: &dyn Intel400xClockHandling = &rom;
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let base_for_clock = clock_handler.get_base();
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assert_eq!(base_for_clock.get_name(), "ROM_4001");
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// Test that data bus trait works
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let data_bus: &dyn Intel400xDataBus = &rom;
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let base_for_data = data_bus.get_base();
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assert_eq!(base_for_data.get_name(), "ROM_4001");
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// Test that address handling trait works
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let address_handler: &dyn Intel400xAddressHandling = &rom;
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let base_for_address = address_handler.get_base();
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assert_eq!(base_for_address.get_name(), "ROM_4001");
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// Test that control pins trait works
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let control_pins: &dyn Intel400xControlPins = &rom;
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let base_for_control = control_pins.get_base();
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assert_eq!(base_for_control.get_name(), "ROM_4001");
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// Test that reset handling trait works
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let reset_handler: &dyn Intel400xResetHandling = &rom;
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let base_for_reset = reset_handler.get_base();
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assert_eq!(base_for_reset.get_name(), "ROM_4001");
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}
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#[test]
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fn test_cross_component_compatibility() {
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// Test that components using the same traits are compatible
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let rom1 = Intel4001::new_with_access_time("ROM1".to_string(), 1);
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let rom2 = Intel4001::new_with_access_time("ROM2".to_string(), 2);
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// Both should implement the same interface
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fn use_intel400x_component(component: &dyn Intel400xTimingState) {
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let _state = component.get_timing_state();
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let _access_time = component.get_access_time();
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}
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use_intel400x_component(&rom1);
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use_intel400x_component(&rom2);
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// Both should have the same initial state
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assert_eq!(rom1.get_timing_state(), rom2.get_timing_state());
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assert_eq!(rom1.get_timing_state(), TimingState::Idle);
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// But different access times
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assert_ne!(rom1.get_access_time(), rom2.get_access_time());
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}
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}
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#[cfg(test)]
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mod cross_component_integration_tests {
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use super::*;
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#[test]
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fn test_multiple_intel4001_components() {
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// Test that multiple Intel4001 components work together
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let mut rom1 = Intel4001::new_with_access_time("ROM1".to_string(), 1);
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let mut rom2 = Intel4001::new_with_access_time("ROM2".to_string(), 2);
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// Load different data into each
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rom1.load_rom_data(vec![0x11, 0x22], 0).unwrap();
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rom2.load_rom_data(vec![0x33, 0x44], 0).unwrap();
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// Both should implement the same traits
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assert_eq!(rom1.read_rom(0x00).unwrap(), 0x11);
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assert_eq!(rom2.read_rom(0x00).unwrap(), 0x33);
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// Both should have the same interface
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assert_eq!(rom1.get_timing_state(), TimingState::Idle);
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assert_eq!(rom2.get_timing_state(), TimingState::Idle);
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// Test state manipulation on both
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rom1.set_timing_state(TimingState::AddressPhase);
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rom2.set_timing_state(TimingState::AddressPhase);
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assert_eq!(rom1.get_timing_state(), TimingState::AddressPhase);
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assert_eq!(rom2.get_timing_state(), TimingState::AddressPhase);
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}
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#[test]
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fn test_timing_consistency_across_components() {
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// Test that timing behavior is consistent across different components
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let mut rom1 = Intel4001::new_with_access_time("ROM1".to_string(), 100);
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let mut rom2 = Intel4001::new_with_access_time("ROM2".to_string(), 200);
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// Both should start with the same timing state
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assert_eq!(rom1.get_timing_state(), rom2.get_timing_state());
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assert_eq!(rom1.get_timing_state(), TimingState::Idle);
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// But have different access times
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assert_eq!(rom1.get_access_time(), 100);
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assert_eq!(rom2.get_access_time(), 200);
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// Both should support the same state transitions
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rom1.set_timing_state(TimingState::AddressPhase);
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rom2.set_timing_state(TimingState::AddressPhase);
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assert_eq!(rom1.get_timing_state(), TimingState::AddressPhase);
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assert_eq!(rom2.get_timing_state(), TimingState::AddressPhase);
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}
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}
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