191 lines
7 KiB
Rust
191 lines
7 KiB
Rust
//! Simple test to verify the intel_400x functionality works
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//!
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//! This is a minimal test that demonstrates the core functionality
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//! without complex mock setups.
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use rusty_emu::components::common::intel_400x::*;
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use rusty_emu::components::memory::intel_4001::Intel4001;
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#[cfg(test)]
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mod simple_tests {
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use super::*;
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#[test]
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fn test_basic_intel400x_functionality() {
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println!("=== Testing Basic Intel 400x Functionality ===");
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// Test 1: Verify timing constants
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println!("\n1. Testing timing constants...");
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assert!(TimingConstants::DEFAULT_ACCESS_TIME > std::time::Duration::from_nanos(0));
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assert!(TimingConstants::FAST_ACCESS_TIME > std::time::Duration::from_nanos(0));
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assert!(TimingConstants::FAST_ACCESS_TIME < TimingConstants::DEFAULT_ACCESS_TIME);
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println!("✓ Timing constants are valid");
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// Test 2: Test state machine
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println!("\n2. Testing state machine...");
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let idle_state = TimingState::Idle;
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let address_state = TimingState::AddressPhase;
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let wait_state = TimingState::WaitLatency;
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let drive_state = TimingState::DriveData;
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assert!(idle_state.is_idle());
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assert!(address_state.is_address_phase());
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assert!(wait_state.is_waiting_latency());
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assert!(drive_state.is_driving_data());
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println!("✓ State machine works correctly");
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// Test 3: Test address assembly logic
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println!("\n3. Testing address assembly...");
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// Test address assembly with different values
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let test_cases = vec![
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(0x00, 0x00, 0x0000),
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(0x12, 0x34, 0x1234),
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(0xFF, 0xFF, 0xFFFF),
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(0x0A, 0x0B, 0x0A0B),
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];
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for (high, low, expected) in test_cases {
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let assembled = ((high as u16) << 4) | (low as u16);
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assert_eq!(assembled, expected);
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}
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println!("✓ Address assembly works correctly");
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// Test 4: Test real component creation
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println!("\n4. Testing real component...");
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let rom = Intel4001::new("TestROM".to_string());
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assert_eq!(rom.get_rom_size(), 256);
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println!("✓ Real component creation works");
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// Test 5: Test data loading and reading
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println!("\n5. Testing data operations...");
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let mut rom = Intel4001::new("DataTestROM".to_string());
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let test_data = vec![0x12, 0x34, 0x56, 0x78];
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rom.load_rom_data(test_data, 0).unwrap();
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assert_eq!(rom.read_rom(0x00).unwrap(), 0x12);
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assert_eq!(rom.read_rom(0x01).unwrap(), 0x34);
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assert_eq!(rom.read_rom(0x02).unwrap(), 0x56);
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assert_eq!(rom.read_rom(0x03).unwrap(), 0x78);
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println!("✓ Data operations work correctly");
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println!("\n=== All basic tests passed! ===");
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println!("The intel_400x common functionality is working correctly.");
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}
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#[test]
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fn test_state_transitions() {
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println!("=== Testing State Transitions ===");
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// Test that state transitions work correctly
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let mut rom = Intel4001::new("StateTestROM".to_string());
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// Test initial state
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assert_eq!(rom.get_timing_state(), TimingState::Idle);
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println!("✓ Initial state is Idle");
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// Test state changes
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rom.set_timing_state(TimingState::AddressPhase);
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assert_eq!(rom.get_timing_state(), TimingState::AddressPhase);
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println!("✓ Can transition to AddressPhase");
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rom.set_timing_state(TimingState::WaitLatency);
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assert_eq!(rom.get_timing_state(), TimingState::WaitLatency);
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println!("✓ Can transition to WaitLatency");
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rom.set_timing_state(TimingState::DriveData);
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assert_eq!(rom.get_timing_state(), TimingState::DriveData);
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println!("✓ Can transition to DriveData");
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// Test return to idle
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rom.set_timing_state(TimingState::Idle);
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assert_eq!(rom.get_timing_state(), TimingState::Idle);
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println!("✓ Can return to Idle");
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println!("=== State transition tests completed ===");
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}
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#[test]
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fn test_address_handling() {
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println!("=== Testing Address Handling ===");
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let mut rom = Intel4001::new("AddressTestROM".to_string());
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// Test address nibble handling
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rom.set_address_high_nibble(Some(0x0F));
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rom.set_address_low_nibble(Some(0x23));
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rom.set_full_address_ready(true);
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assert_eq!(rom.get_address_high_nibble(), Some(0x0F));
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assert_eq!(rom.get_address_low_nibble(), Some(0x23));
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assert_eq!(rom.get_full_address_ready(), true);
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println!("✓ Address nibbles handled correctly");
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// Test clearing address
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rom.set_address_high_nibble(None);
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rom.set_address_low_nibble(None);
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rom.set_full_address_ready(false);
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assert_eq!(rom.get_address_high_nibble(), None);
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assert_eq!(rom.get_address_low_nibble(), None);
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assert_eq!(rom.get_full_address_ready(), false);
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println!("✓ Address clearing works correctly");
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println!("=== Address handling tests completed ===");
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}
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#[test]
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fn test_reset_functionality() {
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println!("=== Testing Reset Functionality ===");
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let mut rom = Intel4001::new("ResetTestROM".to_string());
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// Set up some state
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rom.set_timing_state(TimingState::DriveData);
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rom.set_address_high_nibble(Some(0x12));
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rom.set_address_low_nibble(Some(0x34));
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rom.set_full_address_ready(true);
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// Verify state is set
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assert_eq!(rom.get_timing_state(), TimingState::DriveData);
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assert_eq!(rom.get_address_high_nibble(), Some(0x12));
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assert_eq!(rom.get_address_low_nibble(), Some(0x34));
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assert_eq!(rom.get_full_address_ready(), true);
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println!("✓ State setup completed");
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// Perform reset
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rom.perform_reset();
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// Verify reset behavior
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assert_eq!(rom.get_timing_state(), TimingState::Idle);
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assert_eq!(rom.get_address_high_nibble(), None);
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assert_eq!(rom.get_address_low_nibble(), None);
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assert_eq!(rom.get_full_address_ready(), false);
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println!("✓ Reset functionality works correctly");
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println!("=== Reset tests completed ===");
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}
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#[test]
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fn test_timing_configuration() {
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println!("=== Testing Timing Configuration ===");
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// Test different access times
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let fast_rom = Intel4001::new_with_access_time("FastROM".to_string(), 100);
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let slow_rom = Intel4001::new_with_access_time("SlowROM".to_string(), 1000);
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assert_eq!(fast_rom.get_access_time(), 100);
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assert_eq!(slow_rom.get_access_time(), 1000);
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println!("✓ Different access times configured correctly");
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// Test access time modification
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let mut rom = Intel4001::new("ConfigTestROM".to_string());
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assert_eq!(rom.get_access_time(), 500); // Default
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rom.set_access_time(250);
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assert_eq!(rom.get_access_time(), 250);
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println!("✓ Access time modification works correctly");
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println!("=== Timing configuration tests completed ===");
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}
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}
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