Jan-Peter von Hunnius 80ef0d4475 docs: clean up completed timing plans, add VIC-20 architecture plan ... Remove 6 completed timing architecture phase plans (5-9 + overview). Add comprehensive VIC-20 architecture plan covering: - 6502 CPU family trait hierarchy (MOS 6502, WDC 65C02) - Generic SRAM/ROM memory components - 6560/6561 VIC video chip design - 6522 VIA I/O chip design - Address bus architecture for memory-mapped I/O - Expansion port design - GUI adaptations for multi-system support - 6-phase implementation roadmap		2026-05-14 21:21:46 +02:00
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codebase_analysis.md	feat: Add real-time data display for CPU registers, RAM, and ROM	2026-02-26 19:36:59 +01:00
intel_4004_opcode_fix.md	Fix Intel 4004 CPU emulation bugs: opcode mapping, JCN conditions, DAA carry	2026-05-12 20:55:26 +02:00
observer_pattern_and_ui_layout.md	feat: migrate to parking_lot mutex and add system control architecture	2026-02-28 18:27:27 +01:00
system_control_architecture.md	feat: migrate to parking_lot mutex and add system control architecture	2026-02-28 18:27:27 +01:00
vic20_architecture.md	docs: clean up completed timing plans, add VIC-20 architecture plan	2026-05-14 21:21:46 +02:00