Extracted common 400x behavior like timing and latching into common module Added maxed MCS-4
159 lines
No EOL
6.2 KiB
Rust
159 lines
No EOL
6.2 KiB
Rust
//! Demonstration of running Intel 400x tests
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//!
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//! This module demonstrates how to run the comprehensive test suite
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//! for the intel_400x common functionality.
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use rusty_emu::components::common::intel_400x::*;
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use rusty_emu::components::memory::intel_4001::Intel4001;
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use test_utils::*;
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use test_config::TestConfig;
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#[cfg(test)]
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mod test_demonstration {
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use super::*;
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#[test]
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fn demo_basic_functionality() {
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println!("=== Intel 400x Common Functionality Test Demo ===");
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// Test 1: Verify timing constants
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println!("\n1. Testing timing constants...");
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assert!(TimingConstants::DEFAULT_ACCESS_TIME > std::time::Duration::from_nanos(0));
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assert!(TimingConstants::FAST_ACCESS_TIME > std::time::Duration::from_nanos(0));
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println!("✓ Timing constants are valid");
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// Test 2: Test address assembly
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println!("\n2. Testing address assembly...");
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let mut scenario = create_standard_test_scenario();
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scenario.component.set_address_high_nibble(Some(0x12));
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scenario.component.set_address_low_nibble(Some(0x34));
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scenario.component.set_full_address_ready(true);
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assert_eq!(scenario.component.get_address_high_nibble(), Some(0x12));
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assert_eq!(scenario.component.get_address_low_nibble(), Some(0x34));
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println!("✓ Address assembly works correctly");
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// Test 3: Test state machine
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println!("\n3. Testing state machine...");
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scenario.component.set_timing_state(TimingState::AddressPhase);
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assert_eq!(scenario.component.get_timing_state(), TimingState::AddressPhase);
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assert!(scenario.component.get_timing_state().is_address_phase());
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println!("✓ State machine transitions work correctly");
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// Test 4: Test real component integration
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println!("\n4. Testing real component integration...");
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let mut rom = Intel4001::new_with_access_time("DemoROM".to_string(), 1);
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rom.load_rom_data(vec![0xAB, 0xCD], 0).unwrap();
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assert_eq!(rom.read_rom(0x00).unwrap(), 0xAB);
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assert_eq!(rom.read_rom(0x01).unwrap(), 0xCD);
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println!("✓ Real component integration works");
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// Test 5: Test trait consistency
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println!("\n5. Testing trait consistency...");
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verify_intel400x_traits(&rom);
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println!("✓ All required traits are implemented correctly");
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println!("\n=== All tests passed! ===");
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println!("The intel_400x common functionality is working correctly.");
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}
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#[test]
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fn demo_comprehensive_testing() {
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println!("=== Comprehensive Intel 400x Testing Demo ===");
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// Create test configuration
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let config = TestConfig::default();
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if config.enable_timing_tests {
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println!("\n1. Running timing tests...");
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verify_timing_constants();
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println!("✓ Timing tests completed");
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}
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if config.enable_property_tests {
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println!("\n2. Running property tests...");
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verify_state_machine_properties();
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println!("✓ Property tests completed");
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}
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// Test with different scenarios
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println!("\n3. Testing different scenarios...");
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let mut fast_scenario = crate::mocks::MockScenario::new("FastTest");
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fast_scenario.set_pin_value("SYNC", rusty_emu::pin::PinValue::High);
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fast_scenario.set_pin_value("CM", rusty_emu::pin::PinValue::High);
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fast_scenario.set_pin_value("CI", rusty_emu::pin::PinValue::Low);
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// Test rapid state changes
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for i in 0..10 {
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fast_scenario.component.set_timing_state(TimingState::Idle);
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fast_scenario.component.set_timing_state(TimingState::AddressPhase);
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fast_scenario.component.set_timing_state(TimingState::WaitLatency);
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fast_scenario.component.set_timing_state(TimingState::DriveData);
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}
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assert_eq!(fast_scenario.component.get_timing_state(), TimingState::DriveData);
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println!("✓ Rapid state changes handled correctly");
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// Test data bus operations
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fast_scenario.set_data_bus_value(0x0F);
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assert_eq!(fast_scenario.get_data_bus_value(), 0x0F);
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println!("✓ Data bus operations work correctly");
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println!("\n=== Comprehensive testing completed successfully! ===");
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}
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#[test]
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fn demo_error_handling() {
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println!("=== Error Handling Demo ===");
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// Test graceful error handling
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let mut rom = Intel4001::new("ErrorTestROM".to_string());
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// Test invalid memory access
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assert_eq!(rom.read_rom(0xFF), Some(0x00)); // Default value
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assert_eq!(rom.read_rom(0x100), None); // Out of bounds
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println!("✓ Invalid memory access handled gracefully");
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// Test invalid data loading
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assert!(rom.load_rom_data(vec![0x12], 255).is_ok()); // Valid
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assert!(rom.load_rom_data(vec![0x12], 256).is_err()); // Invalid
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println!("✓ Invalid data loading handled gracefully");
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println!("=== Error handling demo completed ===");
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}
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#[test]
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fn demo_performance_characteristics() {
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println!("=== Performance Characteristics Demo ===");
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// Test that components can handle rapid operations
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let mut rom = Intel4001::new_with_access_time("PerfTestROM".to_string(), 1);
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let start_time = std::time::Instant::now();
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// Perform many state transitions
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for _ in 0..1000 {
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rom.set_timing_state(TimingState::Idle);
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rom.set_timing_state(TimingState::AddressPhase);
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rom.set_timing_state(TimingState::WaitLatency);
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rom.set_timing_state(TimingState::DriveData);
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}
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let elapsed = start_time.elapsed();
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println!("✓ 4000 state transitions completed in {:?}", elapsed);
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// Test address operations
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for i in 0..256 {
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rom.set_address_high_nibble(Some((i >> 4) as u8));
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rom.set_address_low_nibble(Some((i & 0x0F) as u8));
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rom.set_full_address_ready(i % 2 == 0);
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}
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let elapsed = start_time.elapsed();
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println!("✓ 256 address operations completed in {:?}", elapsed);
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println!("=== Performance demo completed ===");
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}
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} |