diff --git a/Cargo.toml b/Cargo.toml
index 5464f47..44f0991 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -2,5 +2,48 @@
 name = "rustysar"
 version = "0.1.0"
 edition = "2021"
+authors = ["Your Name <your.email@example.com>"]
+description = "Infineon Traveo Rust Application"
+categories = ["embedded", "no-std"]
+keywords = ["traveo", "cortex-m", "embedded"]
 
 [dependencies]
+cortex-m = "0.7"
+cortex-m-rt = "0.7"
+embedded-hal = "0.2"
+panic-halt = "0.2"
+nb = "1.0"
+
+# Infineon Traveo specific dependencies
+traveo-hal = { git = "https://github.com/Infineon/traveo-hal.git", optional = true }
+
+[dependencies.cortex-m-semihosting]
+version = "0.5"
+optional = true
+
+[features]
+default = ["rt"]
+rt = ["cortex-m-rt/device"]
+semihosting = ["cortex-m-semihosting"]
+
+# Infineon Traveo specific features
+traveo-cyt2b7 = ["traveo-hal/cyt2b7"]
+traveo-cyt2b9 = ["traveo-hal/cyt2b9"]
+traveo-cyt4bf = ["traveo-hal/cyt4bf"]
+traveo-cyt4dn = ["traveo-hal/cyt4dn"]
+
+[target.thumbv6m-none-eabi.dependencies]
+cortex-m = "0.7"
+
+[target.thumbv7em-none-eabi.dependencies]
+cortex-m = "0.7"
+
+[profile.release]
+codegen-units = 1
+debug = true
+lto = true
+opt-level = "s"
+
+[profile.dev]
+debug = true
+opt-level = "s"
diff --git a/README.md b/README.md
new file mode 100644
index 0000000..5188690
--- /dev/null
+++ b/README.md
@@ -0,0 +1,102 @@
+# Infineon Traveo II Rust Project
+
+This project is configured for developing applications on Infineon Traveo II microcontrollers using Rust.
+
+## Prerequisites
+
+### Required Tools
+
+1. **Rust Toolchain**
+   ```bash
+   rustup target add thumbv6m-none-eabi thumbv7em-none-eabi
+   rustup component add rust-src
+   ```
+
+2. **GNU Arm Embedded Toolchain**
+   - Download from: https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-rm
+   - Install to: `C:\Program Files (x86)\GNU Arm Embedded Toolchain\10 2021.10\`
+   - Add to PATH environment variable
+
+3. **OpenOCD**
+   - Download from: http://openocd.org/
+   - Ensure `openocd.exe` is in your PATH
+
+4. **VSCode Extensions**
+   - Cortex-Debug (marus25.cortex-debug)
+   - Rust Analyzer (rust-lang.rust-analyzer)
+
+## Supported Devices
+
+- **Cortex-M7 devices**: CYT4BF, CYT4DN series
+- **Cortex-M0+ devices**: CYT2B7, CYT2B9 series
+
+## Project Structure
+
+```
+├── .vscode/
+│   ├── launch.json      # Debug configurations
+│   └── tasks.json       # Build tasks
+├── src/
+│   └── main.rs         # Application entry point
+├── memory.x            # Memory configuration (Cortex-M7)
+├── memory-m0.x         # Memory configuration (Cortex-M0+)
+├── build.rs           # Build script
+├── openocd.cfg        # OpenOCD configuration
+├── traveo-cyt4bf.cfg  # CYT4BF target config
+├── traveo-cyt2b7.cfg  # CYT2B7 target config
+└── Cargo.toml         # Project configuration
+```
+
+## Building
+
+### For Cortex-M7 devices (CYT4BF, CYT4DN)
+```bash
+cargo build --target thumbv7em-none-eabi --features traveo-cyt4bf
+```
+
+### For Cortex-M0+ devices (CYT2B7, CYT2B9)
+```bash
+cargo build --target thumbv6m-none-eabi --features traveo-cyt2b7
+```
+
+### Release builds
+```bash
+cargo build --release --target thumbv7em-none-eabi --features traveo-cyt4bf
+```
+
+## Debugging
+
+1. Connect your Traveo II development board
+2. Start OpenOCD:
+   ```bash
+   openocd -f openocd.cfg -f traveo-cyt4bf.cfg
+   ```
+3. In VSCode, use `F5` or go to Run and Debug panel
+4. Select the appropriate debug configuration:
+   - "Debug Traveo (Cortex-M7)" for CYT4BF/CYT4DN
+   - "Debug Traveo (Cortex-M0+)" for CYT2B7/CYT2B9
+
+## Memory Configuration
+
+- **Cortex-M7**: 6MB Flash, 512KB RAM, 64KB TCM
+- **Cortex-M0+**: 2MB Flash, 256KB RAM
+
+## Troubleshooting
+
+1. **OpenOCD not found**: Ensure OpenOCD is installed and in your PATH
+2. **Target not found**: Check that your development board is connected and powered
+3. **Build errors**: Make sure you have the correct target and features selected
+
+## Development Tips
+
+1. Use `panic-halt` for production code (default)
+2. Use `semihosting` feature for debugging output during development
+3. Memory regions can be customized in `memory.x` and `memory-m0.x` files
+4. Add device-specific configurations in the respective `.cfg` files
+
+## Next Steps
+
+1. Update the memory configurations for your specific device
+2. Add device-specific HAL code in `src/main.rs`
+3. Configure OpenOCD for your specific development board
+4. Add any additional dependencies needed for your application
\ No newline at end of file
diff --git a/RUSTROVER_SETUP.md b/RUSTROVER_SETUP.md
new file mode 100644
index 0000000..1a7c079
--- /dev/null
+++ b/RUSTROVER_SETUP.md
@@ -0,0 +1,146 @@
+# RustRover Setup for Infineon Traveo II Debugging
+
+This document provides instructions for setting up RustRover to replicate the VSCode debugging experience for Infineon Traveo II microcontrollers.
+
+## Prerequisites
+
+1. **RustRover IDE** installed
+2. **GNU Arm Embedded Toolchain** installed at `C:/Program Files (x86)/GNU Arm Embedded Toolchain/10 2021.10/bin`
+3. **OpenOCD** installed and available in PATH
+4. **ST-Link debugger** connected to your target hardware
+
+## Project Structure
+
+The converted configurations support two target architectures:
+- **Cortex-M7**: `thumbv7em-none-eabi` with `traveo-cyt4bf` feature
+- **Cortex-M0+**: `thumbv6m-none-eabi` with `traveo-cyt2b7` feature
+
+## Run/Debug Configurations
+
+The following configurations have been created in `.idea/runConfigurations/`:
+
+### Debug Configurations
+
+1. **Debug Traveo (Cortex-M7)**
+   - OpenOCD configuration: `interface/stlink.cfg;target/stm32f7x.cfg`
+   - GDB port: 3333
+   - Builds with: `thumbv7em-none-eabi` target and `traveo-cyt4bf` feature
+
+2. **Debug Traveo (Cortex-M0+)**
+   - OpenOCD configuration: `interface/stlink.cfg;target/stm32f0x.cfg`
+   - GDB port: 3333
+   - Builds with: `thumbv6m-none-eabi` target and `traveo-cyt2b7` feature
+
+3. **Attach to OpenOCD**
+   - For connecting to an already running OpenOCD instance
+   - GDB port: 3333
+
+### Build Configurations
+
+1. **Build Traveo (Cortex-M7)**
+   - Command: `cargo build --target thumbv7em-none-eabi --features traveo-cyt4bf`
+
+2. **Build Traveo (Cortex-M0+)**
+   - Command: `cargo build --target thumbv6m-none-eabi --features traveo-cyt2b7`
+
+## Setup Instructions
+
+### 1. Open Project in RustRover
+1. Launch RustRover
+2. Open the project directory
+3. Ensure Cargo.toml is detected as a Rust project
+
+### 2. Configure Toolchains
+1. Go to **File > Settings > Languages & Frameworks > Rust**
+2. Ensure the correct toolchain is selected for embedded development
+3. Add the GNU Arm Embedded Toolchain to your system PATH if not already present
+
+### 3. Import Run Configurations
+The run configurations are already created in `.idea/runConfigurations/`. They should be automatically detected by RustRover.
+
+### 4. Verify OpenOCD Installation
+1. Open a terminal in RustRover
+2. Run `openocd --version` to verify installation
+3. Ensure ST-Link drivers are installed
+
+### 5. Hardware Setup
+1. Connect your ST-Link debugger to the target board
+2. Ensure proper power supply and connections
+3. Verify the target board is recognized by OpenOCD
+
+## Usage
+
+### Building
+1. Select the appropriate build configuration from the run configurations dropdown
+2. Click the run button or press Shift+F10
+3. The project will build for the selected target architecture
+
+### Debugging
+1. Select the appropriate debug configuration (Cortex-M7 or Cortex-M0+)
+2. Click the debug button or press Shift+F9
+3. RustRover will:
+   - Build the project with the appropriate features
+   - Start OpenOCD with the correct configuration
+   - Launch the debugger and connect to the target
+
+### Attaching to Running OpenOCD
+1. Start OpenOCD manually in a terminal:
+   ```bash
+   openocd -f interface/stlink.cfg -f target/stm32f7x.cfg -c "adapter speed 1000" -c "init" -c "reset init" -c "cortex_m reset_config sysresetreq"
+   ```
+2. Select "Attach to OpenOCD" configuration in RustRover
+3. Click debug to connect to the running OpenOCD instance
+
+## Troubleshooting
+
+### Common Issues
+
+1. **OpenOCD not found**
+   - Ensure OpenOCD is installed and in your system PATH
+   - Restart RustRover after installing OpenOCD
+
+2. **ST-Link not recognized**
+   - Check ST-Link drivers installation
+   - Verify USB connections
+   - Try different USB port
+
+3. **Target not found**
+   - Check target board power and connections
+   - Verify OpenOCD configuration matches your hardware
+   - Check console output for error messages
+
+4. **Build errors**
+   - Ensure all required features are available in Cargo.toml
+   - Check that the correct toolchain is being used
+   - Verify target architecture matches your hardware
+
+### Debug Console
+Open the Debug console in RustRover to see detailed output from OpenOCD and GDB. This can help diagnose connection and configuration issues.
+
+## Advanced Configuration
+
+### Customizing OpenOCD Arguments
+To modify OpenOCD behavior, edit the run configuration and adjust the `OPENOCD_SERVER_ARGS` field:
+
+- Current: `--command "adapter speed 1000" --command "init" --command "reset init" --command "cortex_m reset_config sysresetreq"`
+- Modify adapter speed, initialization commands, or reset configuration as needed
+
+### Adding New Targets
+To add support for additional Traveo II devices:
+
+1. Add the feature to Cargo.toml
+2. Create a new build configuration with the appropriate target and features
+3. Create a corresponding debug configuration with the matching OpenOCD config files
+4. Update this documentation
+
+## Comparison with VSCode
+
+| Feature | VSCode (cortex-debug) | RustRover |
+|---------|----------------------|-----------|
+| Extension/Plugin | cortex-debug extension | Built-in Embedded Development |
+| Configuration | launch.json + tasks.json | XML run configurations |
+| OpenOCD Integration | Through cortex-debug | Native OpenOCD support |
+| Build Integration | Tasks system | Cargo command configurations |
+| Debugging Features | GDB integration | Full GDB debugging support |
+
+The RustRover configurations provide equivalent functionality to the VSCode setup while leveraging RustRover's native embedded development capabilities.
\ No newline at end of file
diff --git a/build.rs b/build.rs
new file mode 100644
index 0000000..a75183c
--- /dev/null
+++ b/build.rs
@@ -0,0 +1,51 @@
+// Build script for Infineon Traveo Rust project
+
+use std::env;
+use std::fs;
+use std::path::Path;
+
+fn main() {
+    // Get the target and feature flags
+    let target = env::var("TARGET").unwrap_or_default();
+    let features = env::var("CARGO_CFG_FEATURES").unwrap_or_default();
+
+    println!("cargo:rerun-if-changed=build.rs");
+    println!("cargo:rerun-if-changed=memory.x");
+    println!("cargo:rerun-if-changed=memory-m0.x");
+
+    // Select appropriate memory configuration based on target
+    let memory_file = if target.contains("thumbv6m") {
+        "memory-m0.x"
+    } else if target.contains("thumbv7em") {
+        "memory.x"
+    } else {
+        "memory.x" // Default to Cortex-M7 config
+    };
+
+    // Check if memory file exists and copy it to output directory
+    if Path::new(memory_file).exists() {
+        println!("cargo:rustc-link-arg-bins=--script={}", memory_file);
+        fs::copy(
+            memory_file,
+            env::var("OUT_DIR").unwrap() + "/" + memory_file,
+        )
+        .expect("Failed to copy memory configuration");
+    }
+
+    // Set up linker script based on target
+    if target.contains("thumbv6m-none-eabi") {
+        println!("cargo:rustc-link-arg=-Tmemory-m0.x");
+        println!("cargo:rustc-link-arg=-Tlink.x");
+    } else if target.contains("thumbv7em-none-eabi") {
+        println!("cargo:rustc-link-arg=-Tmemory.x");
+        println!("cargo:rustc-link-arg=-Tlink.x");
+    }
+
+    // Add target-specific linker arguments
+    println!("cargo:rustc-link-arg=-lc");
+    println!("cargo:rustc-link-arg=-lm");
+    println!("cargo:rustc-link-arg=-lgcc");
+
+    // Set optimization level for embedded development
+    println!("cargo:rustc-env=OPT_LEVEL=s");
+}
diff --git a/memory-m0.x b/memory-m0.x
new file mode 100644
index 0000000..7e04dbd
--- /dev/null
+++ b/memory-m0.x
@@ -0,0 +1,66 @@
+/* Infineon Traveo Memory Configuration for Cortex-M0+ */
+
+/* Memory regions for Cortex-M0+ (Traveo II CYT2B7/CYT2B9) */
+MEMORY
+{
+    FLASH : ORIGIN = 0x10000000, LENGTH = 2112K
+    RAM : ORIGIN = 0x08000000, LENGTH = 256K
+}
+
+/* Stack and heap configuration */
+_stack_start = ORIGIN(RAM) + LENGTH(RAM);
+_heap_size = 32K;
+
+/* Section definitions */
+SECTIONS
+{
+    .vector_table ORIGIN(FLASH) :
+    {
+        KEEP(*(.vector_table));
+    } > FLASH
+
+    .text :
+    {
+        *(.text .text.*);
+    } > FLASH
+
+    .rodata :
+    {
+        *(.rodata .rodata.*);
+        *(.srodata .srodata.*);
+    } > FLASH
+
+    .data : ALIGN(4)
+    {
+        _data_start = .;
+        *(.data .data.*);
+        _data_end = .;
+    } > RAM AT > FLASH
+
+    .bss : ALIGN(4)
+    {
+        _bss_start = .;
+        *(.bss .bss.*);
+        *(COMMON);
+        _bss_end = .;
+    } > RAM
+
+    .uninit : ALIGN(4)
+    {
+        _uninit_start = .;
+        *(.uninit .uninit.*);
+        _uninit_end = .;
+    } > RAM
+
+    /* Discard sections that shouldn't be linked */
+    /DISCARD/ :
+    {
+        *(.ARM.exidx .ARM.exidx.*);
+        *(.ARM.extab .ARM.extab.*);
+    }
+}
+
+/* Stack configuration */
+PROVIDE(_stack_start = ORIGIN(RAM) + LENGTH(RAM));
+PROVIDE(_heap_start = _bss_end);
+PROVIDE(_heap_end = _heap_start + _heap_size);
\ No newline at end of file
diff --git a/memory.x b/memory.x
new file mode 100644
index 0000000..17507d7
--- /dev/null
+++ b/memory.x
@@ -0,0 +1,78 @@
+/* Infineon Traveo Memory Configuration */
+
+/* Memory regions for Cortex-M7 (Traveo II CYT4BF/CYT4DN) */
+MEMORY
+{
+    FLASH : ORIGIN = 0x10000000, LENGTH = 6336K
+    RAM : ORIGIN = 0x08000000, LENGTH = 512K
+    TCM : ORIGIN = 0x00000000, LENGTH = 64K
+}
+
+/* Stack and heap configuration */
+_stack_start = ORIGIN(RAM) + LENGTH(RAM);
+_heap_size = 64K;
+
+/* Section definitions */
+SECTIONS
+{
+    .vector_table ORIGIN(FLASH) :
+    {
+        KEEP(*(.vector_table));
+    } > FLASH
+
+    .text :
+    {
+        *(.text .text.*);
+    } > FLASH
+
+    .rodata :
+    {
+        *(.rodata .rodata.*);
+        *(.srodata .srodata.*);
+    } > FLASH
+
+    .data : ALIGN(4)
+    {
+        _data_start = .;
+        *(.data .data.*);
+        _data_end = .;
+    } > RAM AT > FLASH
+
+    .bss : ALIGN(4)
+    {
+        _bss_start = .;
+        *(.bss .bss.*);
+        *(COMMON);
+        _bss_end = .;
+    } > RAM
+
+    .uninit : ALIGN(4)
+    {
+        _uninit_start = .;
+        *(.uninit .uninit.*);
+        _uninit_end = .;
+    } > RAM
+
+    /* TCM sections for performance-critical code */
+    .tcm_text ORIGIN(TCM) :
+    {
+        *(.tcm_text .tcm_text.*);
+    } > TCM
+
+    .tcm_data :
+    {
+        *(.tcm_data .tcm_data.*);
+    } > TCM
+
+    /* Discard sections that shouldn't be linked */
+    /DISCARD/ :
+    {
+        *(.ARM.exidx .ARM.exidx.*);
+        *(.ARM.extab .ARM.extab.*);
+    }
+}
+
+/* Stack configuration */
+PROVIDE(_stack_start = ORIGIN(RAM) + LENGTH(RAM));
+PROVIDE(_heap_start = _bss_end);
+PROVIDE(_heap_end = _heap_start + _heap_size);
\ No newline at end of file
diff --git a/openocd.cfg b/openocd.cfg
new file mode 100644
index 0000000..0443320
--- /dev/null
+++ b/openocd.cfg
@@ -0,0 +1,37 @@
+# OpenOCD configuration for Infineon Traveo II
+# Generic configuration for Traveo II devices
+
+# Source the interface configuration
+source [find interface/stlink.cfg]
+
+# Traveo II specific target configurations
+# Uncomment the appropriate target based on your device
+
+# For CYT4BF series (Cortex-M7)
+# source [find target/traveo-cyt4bf.cfg]
+
+# For CYT4DN series (Cortex-M7)
+# source [find target/traveo-cyt4dn.cfg]
+
+# For CYT2B7 series (Cortex-M0+)
+# source [find target/traveo-cyt2b7.cfg]
+
+# For CYT2B9 series (Cortex-M0+)
+# source [find target/traveo-cyt2b9.cfg]
+
+# Alternative: Use STM32 configurations for similar cores
+# Cortex-M7 (similar to STM32F7)
+# source [find target/stm32f7x.cfg]
+
+# Cortex-M0+ (similar to STM32F0)
+# source [find target/stm32f0x.cfg]
+
+# Basic adapter speed configuration
+adapter speed 1000
+
+# Initialize and reset
+init
+reset init
+
+# Enable debug access
+cortex_m reset_config sysresetreq
\ No newline at end of file
diff --git a/src/main.rs b/src/main.rs
index e7a11a9..401b56f 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -1,3 +1,45 @@
-fn main() {
-    println!("Hello, world!");
+#![no_std]
+#![no_main]
+
+// Import necessary items from cortex-m-rt and other crates
+use cortex_m_rt::entry;
+use panic_halt as _;
+
+// Optional: Enable semihosting for debugging
+// #[cfg(feature = "semihosting")]
+// use cortex_m_semihosting::{debug, println};
+
+// Entry point for the application
+#[entry]
+fn main() -> ! {
+    // Application initialization code goes here
+
+    // Example: Basic LED blink or other initialization
+    // This is where you would initialize peripherals, clocks, etc.
+
+    // For now, just loop indefinitely
+    loop {
+        // Main application loop
+
+        // Optional: Semihosting debug output (only if feature is enabled)
+        // #[cfg(feature = "semihosting")]
+        // println!("Traveo II application running...");
+
+        // Add a small delay (cortex-m does not have built-in delay)
+        // You would typically use a timer peripheral for this
+
+        // Safety: Continue running indefinitely
+        continue;
+    }
 }
+
+// Optional: Exception handlers for better error handling
+// #[exception]
+// fn HardFault(_ef: &ExceptionFrame) -> ! {
+//     loop {}
+// }
+
+// #[exception]
+// fn DefaultHandler(_irqn: i16) {
+//     loop {}
+// }