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CI: add build workflow (thumbv6m-none-eabi check); remove dead traveo-hal dependency (upstream repo 404, blocked all dependency resolution)
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Jan-Peter von Hunnius 2026-09-01 06:24:59 +02:00
parent c27af61f27
commit b700752fa0
307 changed files with 1068 additions and 9 deletions
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Signature: 8a477f597d28d172789f06886806bc55
# This file is a cache directory tag created by cargo.
# For information about cache directory tags see https://bford.info/cachedir/

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cargo:rustc-check-cfg=cfg(armv6m)
cargo:rustc-check-cfg=cfg(armv7m)
cargo:rustc-check-cfg=cfg(armv7em)
cargo:rustc-check-cfg=cfg(armv8m)
cargo:rustc-check-cfg=cfg(armv8m_base)
cargo:rustc-check-cfg=cfg(armv8m_main)
cargo:rustc-check-cfg=cfg(cortex_m)
cargo:rustc-check-cfg=cfg(has_fpu)
cargo:rustc-check-cfg=cfg(native)
cargo:rustc-cfg=cortex_m
cargo:rustc-cfg=armv6m

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/* # Developer notes
- Symbols that start with a double underscore (__) are considered "private"
- Symbols that start with a single underscore (_) are considered "semi-public"; they can be
overridden in a user linker script, but should not be referred from user code (e.g. `extern "C" {
static mut __sbss }`).
- `EXTERN` forces the linker to keep a symbol in the final binary. We use this to make sure a
symbol is not dropped if it appears in or near the front of the linker arguments and "it's not
needed" by any of the preceding objects (linker arguments)
- `PROVIDE` is used to provide default values that can be overridden by a user linker script
- On alignment: it's important for correctness that the VMA boundaries of both .bss and .data *and*
the LMA of .data are all 4-byte aligned. These alignments are assumed by the RAM initialization
routine. There's also a second benefit: 4-byte aligned boundaries means that you won't see
"Address (..) is out of bounds" in the disassembly produced by `objdump`.
*/
/* Provides information about the memory layout of the device */
/* This will be provided by the user (see `memory.x`) or by a Board Support Crate */
INCLUDE memory.x
/* # Entry point = reset vector */
EXTERN(__RESET_VECTOR);
EXTERN(Reset);
ENTRY(Reset);
/* # Exception vectors */
/* This is effectively weak aliasing at the linker level */
/* The user can override any of these aliases by defining the corresponding symbol themselves (cf.
the `exception!` macro) */
EXTERN(__EXCEPTIONS); /* depends on all the these PROVIDED symbols */
EXTERN(DefaultHandler);
PROVIDE(NonMaskableInt = DefaultHandler);
EXTERN(HardFaultTrampoline);
PROVIDE(MemoryManagement = DefaultHandler);
PROVIDE(BusFault = DefaultHandler);
PROVIDE(UsageFault = DefaultHandler);
PROVIDE(SecureFault = DefaultHandler);
PROVIDE(SVCall = DefaultHandler);
PROVIDE(DebugMonitor = DefaultHandler);
PROVIDE(PendSV = DefaultHandler);
PROVIDE(SysTick = DefaultHandler);
PROVIDE(DefaultHandler = DefaultHandler_);
PROVIDE(HardFault = HardFault_);
/* # Interrupt vectors */
EXTERN(__INTERRUPTS); /* `static` variable similar to `__EXCEPTIONS` */
/* # Pre-initialization function */
/* If the user overrides this using the `pre_init!` macro or by creating a `__pre_init` function,
then the function this points to will be called before the RAM is initialized. */
PROVIDE(__pre_init = DefaultPreInit);
/* # Sections */
SECTIONS
{
PROVIDE(_ram_start = ORIGIN(RAM));
PROVIDE(_ram_end = ORIGIN(RAM) + LENGTH(RAM));
PROVIDE(_stack_start = _ram_end);
/* ## Sections in FLASH */
/* ### Vector table */
.vector_table ORIGIN(FLASH) :
{
__vector_table = .;
/* Initial Stack Pointer (SP) value.
* We mask the bottom three bits to force 8-byte alignment.
* Despite having an assert for this later, it's possible that a separate
* linker script could override _stack_start after the assert is checked.
*/
LONG(_stack_start & 0xFFFFFFF8);
/* Reset vector */
KEEP(*(.vector_table.reset_vector)); /* this is the `__RESET_VECTOR` symbol */
/* Exceptions */
__exceptions = .; /* start of exceptions */
KEEP(*(.vector_table.exceptions)); /* this is the `__EXCEPTIONS` symbol */
__eexceptions = .; /* end of exceptions */
/* Device specific interrupts */
KEEP(*(.vector_table.interrupts)); /* this is the `__INTERRUPTS` symbol */
} > FLASH
PROVIDE(_stext = ADDR(.vector_table) + SIZEOF(.vector_table));
/* ### .text */
.text _stext :
{
__stext = .;
*(.Reset);
*(.text .text.*);
/* The HardFaultTrampoline uses the `b` instruction to enter `HardFault`,
so must be placed close to it. */
*(.HardFaultTrampoline);
*(.HardFault.*);
. = ALIGN(4); /* Pad .text to the alignment to workaround overlapping load section bug in old lld */
__etext = .;
} > FLASH
/* ### .rodata */
.rodata : ALIGN(4)
{
. = ALIGN(4);
__srodata = .;
*(.rodata .rodata.*);
/* 4-byte align the end (VMA) of this section.
This is required by LLD to ensure the LMA of the following .data
section will have the correct alignment. */
. = ALIGN(4);
__erodata = .;
} > FLASH
/* ## Sections in RAM */
/* ### .data */
.data : ALIGN(4)
{
. = ALIGN(4);
__sdata = .;
*(.data .data.*);
. = ALIGN(4); /* 4-byte align the end (VMA) of this section */
} > RAM AT>FLASH
/* Allow sections from user `memory.x` injected using `INSERT AFTER .data` to
* use the .data loading mechanism by pushing __edata. Note: do not change
* output region or load region in those user sections! */
. = ALIGN(4);
__edata = .;
/* LMA of .data */
__sidata = LOADADDR(.data);
/* ### .gnu.sgstubs
This section contains the TrustZone-M veneers put there by the Arm GNU linker. */
/* Security Attribution Unit blocks must be 32 bytes aligned. */
/* Note that this pads the FLASH usage to 32 byte alignment. */
.gnu.sgstubs : ALIGN(32)
{
. = ALIGN(32);
__veneer_base = .;
*(.gnu.sgstubs*)
. = ALIGN(32);
} > FLASH
/* Place `__veneer_limit` outside the `.gnu.sgstubs` section because veneers are
* always inserted last in the section, which would otherwise be _after_ the `__veneer_limit` symbol.
*/
. = ALIGN(32);
__veneer_limit = .;
/* ### .bss */
.bss (NOLOAD) : ALIGN(4)
{
. = ALIGN(4);
__sbss = .;
*(.bss .bss.*);
*(COMMON); /* Uninitialized C statics */
. = ALIGN(4); /* 4-byte align the end (VMA) of this section */
} > RAM
/* Allow sections from user `memory.x` injected using `INSERT AFTER .bss` to
* use the .bss zeroing mechanism by pushing __ebss. Note: do not change
* output region or load region in those user sections! */
. = ALIGN(4);
__ebss = .;
/* ### .uninit */
.uninit (NOLOAD) : ALIGN(4)
{
. = ALIGN(4);
__suninit = .;
*(.uninit .uninit.*);
. = ALIGN(4);
__euninit = .;
} > RAM
/* Align `__sheap` and `_stack_end` pointers to 4 bytes */
. = ALIGN(4);
/* Place the heap start and stack end at the end of allocated RAM */
PROVIDE(__sheap = .);
PROVIDE(_stack_end = .);
/* ## .got */
/* Dynamic relocations are unsupported. This section is only used to detect relocatable code in
the input files and raise an error if relocatable code is found */
.got (NOLOAD) :
{
KEEP(*(.got .got.*));
}
/* ## Discarded sections */
/DISCARD/ :
{
/* Unused exception related info that only wastes space */
*(.ARM.exidx);
*(.ARM.exidx.*);
*(.ARM.extab.*);
}
}
/* Do not exceed this mark in the error messages below | */
/* # Alignment checks */
ASSERT(ORIGIN(FLASH) % 4 == 0, "
ERROR(cortex-m-rt): the start of the FLASH region must be 4-byte aligned");
ASSERT(ORIGIN(RAM) % 4 == 0, "
ERROR(cortex-m-rt): the start of the RAM region must be 4-byte aligned");
ASSERT(__sdata % 4 == 0 && __edata % 4 == 0, "
BUG(cortex-m-rt): .data is not 4-byte aligned");
ASSERT(__sidata % 4 == 0, "
BUG(cortex-m-rt): the LMA of .data is not 4-byte aligned");
ASSERT(__sbss % 4 == 0 && __ebss % 4 == 0, "
BUG(cortex-m-rt): .bss is not 4-byte aligned");
ASSERT(__sheap % 4 == 0, "
BUG(cortex-m-rt): start of .heap is not 4-byte aligned");
ASSERT(_stack_start % 8 == 0, "
ERROR(cortex-m-rt): stack start address is not 8-byte aligned.
If you have set _stack_start, check it's set to an address which is a multiple of 8 bytes.
If you haven't, stack starts at the end of RAM by default. Check that both RAM
origin and length are set to multiples of 8 in the `memory.x` file.");
ASSERT(_stack_end % 4 == 0, "
ERROR(cortex-m-rt): end of stack is not 4-byte aligned");
ASSERT(_stack_start >= _stack_end, "
ERROR(cortex-m-rt): stack end address is not below stack start.");
/* # Position checks */
/* ## .vector_table
*
* If the *start* of exception vectors is not 8 bytes past the start of the
* vector table, then we somehow did not place the reset vector, which should
* live 4 bytes past the start of the vector table.
*/
ASSERT(__exceptions == ADDR(.vector_table) + 0x8, "
BUG(cortex-m-rt): the reset vector is missing");
ASSERT(__eexceptions == ADDR(.vector_table) + 0x40, "
BUG(cortex-m-rt): the exception vectors are missing");
ASSERT(SIZEOF(.vector_table) > 0x40, "
ERROR(cortex-m-rt): The interrupt vectors are missing.
Possible solutions, from most likely to less likely:
- Link to a svd2rust generated device crate
- Check that you actually use the device/hal/bsp crate in your code
- Disable the 'device' feature of cortex-m-rt to build a generic application (a dependency
may be enabling it)
- Supply the interrupt handlers yourself. Check the documentation for details.");
ASSERT(ADDR(.vector_table) % MAX(128, 1 << LOG2CEIL(SIZEOF(.vector_table))) == 0, "
ERROR(cortex-m-rt): Interrupt vector table misalignment detected. The vector table must
be aligned to the larger of:
- 128 bytes
- The next power of two greater than or equal to its size");
/* ## .text */
ASSERT(ADDR(.vector_table) + SIZEOF(.vector_table) <= _stext, "
ERROR(cortex-m-rt): The .text section can't be placed inside the .vector_table section
Set _stext to an address greater than the end of .vector_table (See output of `nm`)");
ASSERT(_stext >= ORIGIN(FLASH) && _stext < ORIGIN(FLASH) + LENGTH(FLASH), "
ERROR(cortex-m-rt): The .text section must be placed inside the FLASH memory.
Set _stext to an address within the FLASH region.");
/* # Other checks */
ASSERT(SIZEOF(.got) == 0, "
ERROR(cortex-m-rt): .got section detected in the input object files
Dynamic relocations are not supported. If you are linking to C code compiled using
the 'cc' crate then modify your build script to compile the C code _without_
the -fPIC flag. See the documentation of the `cc::Build.pic` method for details.");
/* Do not exceed this mark in the error messages above | */
/* Provides weak aliases (cf. PROVIDED) for device specific interrupt handlers */
/* This will usually be provided by a device crate generated using svd2rust (see `device.x`) */
INCLUDE device.x
ASSERT(SIZEOF(.vector_table) <= 0xc0, "
There can't be more than 32 interrupt handlers. This may be a bug in
your device crate, or you may have registered more than 32 interrupt
handlers.");

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cargo:rustc-check-cfg=cfg(armv6m)
cargo:rustc-check-cfg=cfg(armv7em)
cargo:rustc-check-cfg=cfg(armv7m)
cargo:rustc-check-cfg=cfg(armv8m)
cargo:rustc-check-cfg=cfg(armv8m_base)
cargo:rustc-check-cfg=cfg(armv8m_main)
cargo:rustc-check-cfg=cfg(cortex_m)
cargo:rustc-check-cfg=cfg(has_fpu)
cargo:rustc-cfg=cortex_m
cargo:rustc-cfg=armv6m
cargo:rustc-link-search=/home/jan/RustroverProjects/rustysar/target/thumbv6m-none-eabi/debug/build/cortex-m-rt-cc32282c29a5e8bc/out
cargo:rerun-if-changed=build.rs
cargo:rerun-if-changed=link.x.in

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/* Infineon Traveo Memory Configuration for Cortex-M0+ */
/* Memory regions for Cortex-M0+ (Traveo II CYT2B7/CYT2B9) */
MEMORY
{
FLASH : ORIGIN = 0x10000000, LENGTH = 2112K
RAM : ORIGIN = 0x08000000, LENGTH = 256K
}
/* Stack and heap configuration */
_stack_start = ORIGIN(RAM) + LENGTH(RAM);
_heap_size = 32K;
/* Section definitions */
SECTIONS
{
.vector_table ORIGIN(FLASH) :
{
KEEP(*(.vector_table));
} > FLASH
.text :
{
*(.text .text.*);
} > FLASH
.rodata :
{
*(.rodata .rodata.*);
*(.srodata .srodata.*);
} > FLASH
.data : ALIGN(4)
{
_data_start = .;
*(.data .data.*);
_data_end = .;
} > RAM AT > FLASH
.bss : ALIGN(4)
{
_bss_start = .;
*(.bss .bss.*);
*(COMMON);
_bss_end = .;
} > RAM
.uninit : ALIGN(4)
{
_uninit_start = .;
*(.uninit .uninit.*);
_uninit_end = .;
} > RAM
/* Discard sections that shouldn't be linked */
/DISCARD/ :
{
*(.ARM.exidx .ARM.exidx.*);
*(.ARM.extab .ARM.extab.*);
}
}
/* Stack configuration */
PROVIDE(_stack_start = ORIGIN(RAM) + LENGTH(RAM));
PROVIDE(_heap_start = _bss_end);
PROVIDE(_heap_end = _heap_start + _heap_size);

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cargo:rerun-if-changed=build.rs
cargo:rerun-if-changed=memory.x
cargo:rerun-if-changed=memory-m0.x
cargo:rustc-link-arg-bins=--script=memory-m0.x
cargo:rustc-link-arg=-Tmemory-m0.x
cargo:rustc-link-arg=-Tlink.x
cargo:rustc-link-arg=-lc
cargo:rustc-link-arg=-lm
cargo:rustc-link-arg=-lgcc
cargo:rustc-env=OPT_LEVEL=s

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/home/jan/RustroverProjects/rustysar/target/thumbv6m-none-eabi/debug/deps/libbare_metal-403e07080418254b.rmeta: /home/jan/.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/bare-metal-0.2.5/src/lib.rs
/home/jan/.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/bare-metal-0.2.5/src/lib.rs:

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/home/jan/RustroverProjects/rustysar/target/thumbv6m-none-eabi/debug/deps/libbitfield-a9b55d61be9b0606.rmeta: /home/jan/.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/bitfield-0.13.2/src/lib.rs
/home/jan/.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/bitfield-0.13.2/src/lib.rs:

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/home/jan/RustroverProjects/rustysar/target/thumbv6m-none-eabi/debug/deps/cortex_m-4dc7115877a4695e.d: /home/jan/.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/cortex-m-0.7.9/src/lib.rs /home/jan/.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/cortex-m-0.7.9/src/macros.rs /home/jan/.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/cortex-m-0.7.9/src/asm.rs /home/jan/.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/cortex-m-0.7.9/src/delay.rs /home/jan/.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/cortex-m-0.7.9/src/interrupt.rs /home/jan/.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/cortex-m-0.7.9/src/peripheral/mod.rs /home/jan/.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/cortex-m-0.7.9/src/peripheral/cpuid.rs /home/jan/.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/cortex-m-0.7.9/src/peripheral/dcb.rs /home/jan/.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/cortex-m-0.7.9/src/peripheral/dwt.rs /home/jan/.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/cortex-m-0.7.9/src/peripheral/icb.rs /home/jan/.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/cortex-m-0.7.9/src/peripheral/mpu.rs /home/jan/.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/cortex-m-0.7.9/src/peripheral/nvic.rs /home/jan/.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/cortex-m-0.7.9/src/peripheral/scb.rs /home/jan/.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/cortex-m-0.7.9/src/peripheral/syst.rs /home/jan/.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/cortex-m-0.7.9/src/prelude.rs /home/jan/.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/cortex-m-0.7.9/src/psp.rs /home/jan/.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/cortex-m-0.7.9/src/register/mod.rs /home/jan/.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/cortex-m-0.7.9/src/register/control.rs /home/jan/.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/cortex-m-0.7.9/src/register/msp.rs /home/jan/.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/cortex-m-0.7.9/src/register/primask.rs /home/jan/.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/cortex-m-0.7.9/src/register/psp.rs /home/jan/.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/cortex-m-0.7.9/src/register/apsr.rs /home/jan/.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/cortex-m-0.7.9/src/register/lr.rs /home/jan/.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/cortex-m-0.7.9/src/register/pc.rs
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