66 lines
No EOL
1.3 KiB
Text
66 lines
No EOL
1.3 KiB
Text
/* Infineon Traveo Memory Configuration for Cortex-M0+ */
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/* Memory regions for Cortex-M0+ (Traveo II CYT2B7/CYT2B9) */
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MEMORY
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{
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FLASH : ORIGIN = 0x10000000, LENGTH = 2112K
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RAM : ORIGIN = 0x08000000, LENGTH = 256K
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}
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/* Stack and heap configuration */
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_stack_start = ORIGIN(RAM) + LENGTH(RAM);
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_heap_size = 32K;
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/* Section definitions */
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SECTIONS
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{
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.vector_table ORIGIN(FLASH) :
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{
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KEEP(*(.vector_table));
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} > FLASH
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.text :
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{
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*(.text .text.*);
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} > FLASH
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.rodata :
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{
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*(.rodata .rodata.*);
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*(.srodata .srodata.*);
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} > FLASH
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.data : ALIGN(4)
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{
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_data_start = .;
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*(.data .data.*);
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_data_end = .;
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} > RAM AT > FLASH
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.bss : ALIGN(4)
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{
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_bss_start = .;
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*(.bss .bss.*);
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*(COMMON);
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_bss_end = .;
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} > RAM
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.uninit : ALIGN(4)
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{
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_uninit_start = .;
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*(.uninit .uninit.*);
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_uninit_end = .;
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} > RAM
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/* Discard sections that shouldn't be linked */
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/DISCARD/ :
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{
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*(.ARM.exidx .ARM.exidx.*);
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*(.ARM.extab .ARM.extab.*);
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}
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}
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/* Stack configuration */
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PROVIDE(_stack_start = ORIGIN(RAM) + LENGTH(RAM));
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PROVIDE(_heap_start = _bss_end);
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PROVIDE(_heap_end = _heap_start + _heap_size); |