78 lines
No EOL
1.5 KiB
Text
78 lines
No EOL
1.5 KiB
Text
/* Infineon Traveo Memory Configuration */
|
|
|
|
/* Memory regions for Cortex-M7 (Traveo II CYT4BF/CYT4DN) */
|
|
MEMORY
|
|
{
|
|
FLASH : ORIGIN = 0x10000000, LENGTH = 6336K
|
|
RAM : ORIGIN = 0x08000000, LENGTH = 512K
|
|
TCM : ORIGIN = 0x00000000, LENGTH = 64K
|
|
}
|
|
|
|
/* Stack and heap configuration */
|
|
_stack_start = ORIGIN(RAM) + LENGTH(RAM);
|
|
_heap_size = 64K;
|
|
|
|
/* Section definitions */
|
|
SECTIONS
|
|
{
|
|
.vector_table ORIGIN(FLASH) :
|
|
{
|
|
KEEP(*(.vector_table));
|
|
} > FLASH
|
|
|
|
.text :
|
|
{
|
|
*(.text .text.*);
|
|
} > FLASH
|
|
|
|
.rodata :
|
|
{
|
|
*(.rodata .rodata.*);
|
|
*(.srodata .srodata.*);
|
|
} > FLASH
|
|
|
|
.data : ALIGN(4)
|
|
{
|
|
_data_start = .;
|
|
*(.data .data.*);
|
|
_data_end = .;
|
|
} > RAM AT > FLASH
|
|
|
|
.bss : ALIGN(4)
|
|
{
|
|
_bss_start = .;
|
|
*(.bss .bss.*);
|
|
*(COMMON);
|
|
_bss_end = .;
|
|
} > RAM
|
|
|
|
.uninit : ALIGN(4)
|
|
{
|
|
_uninit_start = .;
|
|
*(.uninit .uninit.*);
|
|
_uninit_end = .;
|
|
} > RAM
|
|
|
|
/* TCM sections for performance-critical code */
|
|
.tcm_text ORIGIN(TCM) :
|
|
{
|
|
*(.tcm_text .tcm_text.*);
|
|
} > TCM
|
|
|
|
.tcm_data :
|
|
{
|
|
*(.tcm_data .tcm_data.*);
|
|
} > TCM
|
|
|
|
/* Discard sections that shouldn't be linked */
|
|
/DISCARD/ :
|
|
{
|
|
*(.ARM.exidx .ARM.exidx.*);
|
|
*(.ARM.extab .ARM.extab.*);
|
|
}
|
|
}
|
|
|
|
/* Stack configuration */
|
|
PROVIDE(_stack_start = ORIGIN(RAM) + LENGTH(RAM));
|
|
PROVIDE(_heap_start = _bss_end);
|
|
PROVIDE(_heap_end = _heap_start + _heap_size); |