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0e0713c3a0
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Fixed test failures
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2025-09-30 10:23:17 +02:00 |
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c8552a1488
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Separated two-phase clock from generic clock
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2025-09-30 07:22:48 +02:00 |
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7d06837608
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Added I/O demo system
CLean up of unused components and functions
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2025-09-29 21:42:37 +02:00 |
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0278a96a8d
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Added console for displaying the system state
Corrected behaviour and tests
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2025-09-29 19:02:00 +02:00 |
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6f3295dc5e
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Created factory for system creation.
Systems are now defined in JSON rather than hard-coded
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2025-09-29 12:41:16 +02:00 |
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c039e9069a
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Added more tests
Extracted common 400x behavior like timing and latching into common module
Added maxed MCS-4
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2025-09-29 11:53:46 +02:00 |
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e7c98f0c47
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Implemented Intel 4003
Completed instruction set of 4004
Improved accuracy of 4002 and 4004 implementations
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2025-09-28 20:31:12 +02:00 |
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cff459d2b5
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Rust code formatter
Added threaded RunnableComponent trait
Accurate, threaded implementation of the 4001 ROM
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2025-09-27 19:23:31 +02:00 |
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3c85ed2b00
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Fix for last ram bank
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2025-09-24 16:50:20 +02:00 |
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e64d3edbd8
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Sleep time for threads extended
Fix for ActiveBus check (thread did not run)
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2025-09-24 15:13:17 +02:00 |
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f66f4c5d6c
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Fixes for concurrency and the fibonacci example
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2025-09-24 09:44:18 +02:00 |
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7dd09c730d
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Re-implementations of all Intel 400x chips.
The MCS-4 is still broken, so are the 6502 chips
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2025-09-22 19:32:44 +02:00 |
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ba1b0ddc22
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More flexible bus system that takes VIC-20 address mapping and multiplexed buses like the MCS-4 into account.
Broken currently, subject to fixes
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2025-09-22 17:48:16 +02:00 |
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