08f53d68fe
feat: implement virtual clock timing architecture (Phases 5-8)
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Introduces a VirtualClock-based timing system replacing wall-clock
Instant-based timing for hardware-accurate simulation.
New modules:
- virtual_clock.rs: Shared virtual time source with condvar sync
- real_time_governor.rs: Thread that advances virtual time
- component_timing.rs: Per-component timing constraints
Key changes:
- Component trait: added update_at_time(), timing(), set_virtual_clock_optional()
- All Intel 400x components migrated to virtual-time-aware operation
- ConfigurableSystem: start() returns Result, spawns governor thread
- GUI: timing controls (speed slider, mode selector, step button)
- Console: speed/mode/step/time commands
- Backward compatible: legacy fallback for components without VirtualClock
Reviewed-by: code review found 2 warnings (clock resume() dead code,
reset() safety docs) — both fixed.
2026-05-14 21:00:22 +02:00
6a335a15d4
Fix Intel 4004 CPU instruction set and improve MCS-4 timing accuracy
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Overhaul the Intel 4004 instruction set to match the real opcode map,
adding missing instructions (NOP, FIM, FIN, JIN, ISZ, KBP, DCL, WR0-3,
RD0-3) and refining two-byte instruction handling with proper M1/M2
data phases. Rewrite the CPU fetch-execute cycle to correctly process
two-byte opcodes across separate clock cycles.
Improve Intel 4001 ROM timing with M1/M2 nibble phase tracking and an
A3 wait counter so the ROM drives data only when the CPU expects it.
Fix state-machine transition helpers in Intel 4002 and 4003 to capture
the old state before processing events, preventing incorrect exit/entry
callbacks.
Add non-propagating pin driver methods to prevent deadlocks caused by
bidirectional pin connections during signal propagation.
Add Fibonacci integration test and opcode fix plan document.
Update all README files to reflect the new instruction set.
2026-05-12 19:32:01 +02:00
54144d10e9
feat: migrate to parking_lot mutex and add system control architecture
2026-02-28 18:27:27 +01:00
6e245b615e
chore: remove debug logging statements and fix clock propagation
2026-02-26 20:07:05 +01:00
6636417d18
feat: Add real-time data display for CPU registers, RAM, and ROM
2026-02-26 19:36:59 +01:00
c9f39aa600
fix: RESET pin active-LOW and clock edge state reset
2026-02-26 11:04:25 +01:00
1cf2cd6e2b
fix: address latching timing and cleanup debug code
2026-02-25 11:55:16 +01:00
20884b57c3
feat(cpu): add A1/A2/A3 address cycle timing and fix pin propagation
2026-02-24 18:58:14 +01:00
633463e370
Unified the 400x state machine for address latching
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Fixed timing issues
2025-11-14 18:51:10 +01:00
e17d6ad177
Added debug output
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Added GUI
2025-10-03 11:44:55 +02:00
3d4de8b268
Syntax cleanup, fixed never-ending test suite (console in doc-test)
2025-09-30 11:43:49 +02:00
f46cde7ef0
Completed Intel 4004 CPU implementation
2025-09-30 10:44:14 +02:00
0e0713c3a0
Fixed test failures
2025-09-30 10:23:17 +02:00
c8552a1488
Separated two-phase clock from generic clock
2025-09-30 07:22:48 +02:00
7d06837608
Added I/O demo system
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CLean up of unused components and functions
2025-09-29 21:42:37 +02:00
0278a96a8d
Added console for displaying the system state
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Corrected behaviour and tests
2025-09-29 19:02:00 +02:00
6f3295dc5e
Created factory for system creation.
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Systems are now defined in JSON rather than hard-coded
2025-09-29 12:41:16 +02:00
c039e9069a
Added more tests
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Extracted common 400x behavior like timing and latching into common module
Added maxed MCS-4
2025-09-29 11:53:46 +02:00
e7c98f0c47
Implemented Intel 4003
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Completed instruction set of 4004
Improved accuracy of 4002 and 4004 implementations
2025-09-28 20:31:12 +02:00
5bc1916b2f
Introduced comments to some files
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Improved accuracy and test of the Intel 4001 ROM.
Tests currently fail on the 4001.
2025-09-27 21:37:54 +02:00
cff459d2b5
Rust code formatter
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Added threaded RunnableComponent trait
Accurate, threaded implementation of the 4001 ROM
2025-09-27 19:23:31 +02:00
e64d3edbd8
Sleep time for threads extended
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Fix for ActiveBus check (thread did not run)
2025-09-24 15:13:17 +02:00
974fa25a3c
Fixed borrow issues
2025-09-24 13:52:35 +02:00
f66f4c5d6c
Fixes for concurrency and the fibonacci example
2025-09-24 09:44:18 +02:00
7dd09c730d
Re-implementations of all Intel 400x chips.
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The MCS-4 is still broken, so are the 6502 chips
2025-09-22 19:32:44 +02:00
e69c549750
Bug Fixes
2025-09-22 18:40:13 +02:00
ba1b0ddc22
More flexible bus system that takes VIC-20 address mapping and multiplexed buses like the MCS-4 into account.
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Broken currently, subject to fixes
2025-09-22 17:48:16 +02:00
