Carry-over Infineon basis

memory-m0.x

@@ -0,0 +1,66 @@
+/* Infineon Traveo Memory Configuration for Cortex-M0+ */
+
+/* Memory regions for Cortex-M0+ (Traveo II CYT2B7/CYT2B9) */
+MEMORY
+{
+    FLASH : ORIGIN = 0x10000000, LENGTH = 2112K
+    RAM : ORIGIN = 0x08000000, LENGTH = 256K
+}
+
+/* Stack and heap configuration */
+_stack_start = ORIGIN(RAM) + LENGTH(RAM);
+_heap_size = 32K;
+
+/* Section definitions */
+SECTIONS
+{
+    .vector_table ORIGIN(FLASH) :
+    {
+        KEEP(*(.vector_table));
+    } > FLASH
+
+    .text :
+    {
+        *(.text .text.*);
+    } > FLASH
+
+    .rodata :
+    {
+        *(.rodata .rodata.*);
+        *(.srodata .srodata.*);
+    } > FLASH
+
+    .data : ALIGN(4)
+    {
+        _data_start = .;
+        *(.data .data.*);
+        _data_end = .;
+    } > RAM AT > FLASH
+
+    .bss : ALIGN(4)
+    {
+        _bss_start = .;
+        *(.bss .bss.*);
+        *(COMMON);
+        _bss_end = .;
+    } > RAM
+
+    .uninit : ALIGN(4)
+    {
+        _uninit_start = .;
+        *(.uninit .uninit.*);
+        _uninit_end = .;
+    } > RAM
+
+    /* Discard sections that shouldn't be linked */
+    /DISCARD/ :
+    {
+        *(.ARM.exidx .ARM.exidx.*);
+        *(.ARM.extab .ARM.extab.*);
+    }
+}
+
+/* Stack configuration */
+PROVIDE(_stack_start = ORIGIN(RAM) + LENGTH(RAM));
+PROVIDE(_heap_start = _bss_end);
+PROVIDE(_heap_end = _heap_start + _heap_size);